GPUSTAT and GPUREAD

Status register and read port of the GPU at 0x1F801814 and 0x1F801810.

Summary

The GPU has two I/O ports. A read from 0x1F801814 (GP1) returns the status register, called GPUSTAT here, and a read from 0x1F801810 (GP0) returns GPUREAD, which receives the data of GP0(C0h) and the registers selected by GP1(10h).¹ GPUSTAT shows most of the settings made by GP0(E1h), GP0(E6h) and GP1 commands, together with the FIFO, DMA and interlace state.²

The bit names are those that psx-spx takes from the debug symbols of the PlayStation 2 SDK version 2.8, which emulates this register; some of them also appear in PlayStation libraries.² The GPUSTAT value after GP1(00h) is 14802000h.³

Data Request Bit

The meaning of bit 25 depends on the DMA direction set by GP1(04h):²

Bit 25 is the DMA request signal. However, it is also useful for transfers by software and in particular for the FIFO state mode (direction 1).⁴

Ready Bits

Bit 28 is cleared while a command is executing, that is, once the command and all its parameters have been received. For polygon and line commands, however, it is cleared as soon as the command word arrives and before the vertices are sent. Because DMA direction 2 uses this bit as its request, a DMA transfer would probably stall if the vertices of a polygon or line were sent in a separate DMA block.⁴

Bit 27 is set after GP0(C0h) and its parameters have been sent, and it stays set until all data words have been read; DMA direction 3 uses it as its request.⁴ Bit 26 is set when the GPU can accept a new command. When it is clear, the GPU is waiting for more parameters or data, or it is busy. Bit 26 rises briefly after each primitive, so it cannot show when the GPU has finished a whole DMA chain of primitives.⁴

In libgpu, DrawSync(0) blocks until all requests in the queue are finished and DrawSync(1) returns the number of requests remaining.⁵

Interlace Field

In 480-line interlaced mode bit 31 changes with each field, and in 240-line mode it changes with each scanline. It is always 0 during vertical blanking.²

Sony explains why the bit matters. In interlace mode the GPU draws only the even lines while the odd field is displayed and only the odd lines while the even field is displayed, so a single buffer can be drawn while it is shown. However, during the vertical blank the GPU always treats the field as even. Primitives drawn during the vertical blank, which in Z-sorted drawing are the background, therefore reach only the even lines, and half the background is not cleared.⁶⁷

The remedy is to start drawing after the vertical blank has ended. Libgpu provides GetODE() for this, and the function was formally introduced in library version 3.7. GetODE() returns the field that the GPU recognizes, not the field of the current video output; during the vertical blank after VSyncCallback() it returns even.⁷

GPUREAD

GPUREAD at 0x1F801810 returns the data of a VRAM-to-CPU transfer started by GP0(C0h), or the register latched by GP1(10h). It can also be read by DMA channel 2.¹ The GP0 transfer page and the GP1 page describe the two commands.

References