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Hardware tests

Hardware Behavior Checks

Measures twelve separate points of timer, DMA, GTE, MDEC, SPU, controller port, GPU and CD-ROM behavior.

Hardware Behavior Checks
MachineSCPH-5501
Programfollowup

Overview

The program runs twelve groups, and each group asks one question. Root counter 2 at 33.8688 MHz is the stopwatch throughout, and each group puts the timers' modes and targets and I_MASK back when it ends.1

Table 1: Groups
Tag Group
FTS Timer 2 stopped in sync mode 0: which counter writes set the reached-target bit
FTM The counter read at once after a mode write
FVB When timer 1 in sync mode 1 resets after the vertical blank interrupt
FDI How soon a forced DICR interrupt reaches I_STAT
FGT GTE: IR0 at the edge of its range, and every opcode 00h to 3Fh
FMD MDEC: status after a reset, short decode counts, and the colour conversion of DC-only blocks
FSP SPU: the envelope counter, level writes, the transfer FIFO and a start address inside a block
FDS DMA4 to the SPU by block size and SPU delay setting
FSI The controller port with receive enabled and nothing selected, and I_MASK's upper half
FGR GPU: offset wrap, GP1(10h) indices 2 and 3, the GP0(C0h) pad, CLUT rows and unwaited GP0 stores
FCD CD-ROM with no disc: an invalid command, Init and Reset
FMR MDEC by DMA after a reset, and a store to a full input FIFO

FGR, FCD and FMR each hold a step that could stop the console, so they run last and save their log before that step. The later cards ran the safe groups in one program (followup_safe) and each risky group in its own (followup_fcd, followup_fgr, followup_fmr1 and followup_fmr2).1

Results

Timers

With timer 2 stopped (mode 0001h) and target 8000h, writing the counter 8000h set bit 11 of the mode (it read 0C01h). Writing 1234h, 7FFFh, 8001h, FFFFh or 0000h left the mode at 0401h. With target 1234h, a counter write of 1234h set bit 11 and 1233h did not.1 A counter read straight after a mode write gave 0 in all eight reads, for timers 0, 1 and 2 on the 33.8688 MHz clock, timer 1 on horizontal blank and timer 0 on the dot clock.1

Timer 1 in sync mode 1 on the 33.8688 MHz clock reset 49,462 to 49,498 cycles after the vertical blank interrupt. The first value after the reset was 22 to 31. On horizontal blank it read 24 and then reset to 0 at 52,021 to 52,044 cycles after the interrupt. Free running on horizontal blank it counted 263 from one vertical blank interrupt to the next.1

DMA Interrupt

With IRQ3 masked, a write of 00008000h to DICR set I_STAT bit 3 by the second read, 39 cycles after the write; the first read at 9 cycles still showed 0. A write of 0 left the bit clear.1

GTE

RTPS with sf 1, DQA 0 and DQB 1000000h gave IR0 1000h and FLAG 0. DQB 0FFFFFFh gave IR0 FFFh. DQB 1000FFFh gave IR0 1000h with FLAG bit 12 set. IR0 therefore saturates at 1000h.1

The program then ran every opcode 00h to 3Fh with sf 1 and sf 0 on one set of seeded inputs and printed the registers each changed. That table is in the output below.1

MDEC

After a reset write of 80000000h to MDEC1 the status read 80040000h at the first read 14 cycles later. With a 15-bit decode's input full the first read at 14 cycles still gave E60400DFh. The second read at 43 cycles gave 80040000h.1

An 8-bit decode with a count of 1 gave 48 output words and a count of 2 gave 32. A 15-bit decode with counts of 4, 5 and 6 gave 32 words of zero.1

For one macroblock of DC-only blocks with all quant values 4, the first output word of each quadrant was the same in all four quadrants. With Cr, Cb and Y all 0 the 24-bit output was 80808080h and the 15-bit output 42104210h. Y of -128 gave 40404040h and Y of 127 gave BFBFBFBFh. At the ends of the Cr and Cb range the components stopped at 00h and FFh: Cr 255 and Cb 255 with Y 0 gave FFFF00FFh.1

SPU

Voices 0 and 1, keyed on about 1600 cycles apart with the same linear attack, changed level at the same moments: 8,029, 32,589, 57,229 and 81,797 cycles after voice 0's key on in the first run. The two voices therefore share one envelope counter.1

A level written as 4000h or 7FFFh read back the same value. Before the write the level read 3FFFh.1

After a 16-word DMA block to sound RAM and SPUCNT set to Stop, 8 of the 32 halfwords had reached sound RAM at once. About 4 more arrived every 100 cycles, and all 32 were there 800 cycles after the DMA ended.1

A voice started at 40C0h played silence. Started one 8-byte unit later at 40C1h, it played the block's samples.1

DMA4 Block Size

A 256-word DMA4 write to the SPU took 16,281 to 18,283 cycles in blocks of 1 to 16 words and about 8,500 cycles in blocks of 32 words. Raising bits 24 to 27 of the SPU delay register (1F801014h) from 0 to 3 made the 32-word transfer take up to 10,196 cycles.1

Table 2: DMA4 write of 256 words in cycles (first of three)
SPU delay 1 word 2 words 4 words 8 words 16 words 32 words
200931E1h 16,343 16,312 18,283 17,029 16,846 8,515
210931E1h 16,350 17,236 18,317 17,927 17,544 8,621
220931E1h 16,368 19,534 18,325 18,631 17,759 9,488
230931E1h 16,376 19,592 19,441 18,699 17,819 10,196

Controller Port and I_MASK

With JOY_CTRL 0004h (receive enabled, no device selected) and no data written, JOY_STAT read 005h and changed to 007h about 1300 cycles later. One byte, FFh, was then in the receive FIFO. With JOY_CTRL 0805h it changed to 207h and I_STAT bit 7 was set.1

After a store of 12345678h to I_MASK the low 11 bits read 678h. The upper half read AD09h, and AE02h after an I_STAT load in between, so it does not hold the value written.1

GPU

A 16-pixel tile drew at offset 0 and vertex x 76. With offset plus vertex at 1100, from offset 500 and vertex 600 or from offset 1000 and vertex 100, nothing was drawn in the window at x 64 to 95.1

GP1(10h) index 2 after GP0(E2h) FFFFFFh read 000FFFFFh. After a GP0(C0h) VRAM read of the pixels 1230h to 1233h it read 123FFFFFh, and index 3 after GP0(E3h) FFFFFFh read 123FFFFFh as well. The same values came back with the texture page at 512,256 and at 768,256.1

A 3 by 1 GP0(C0h) read gave a fourth halfword of pad. With row 408 holding 2220h to 2227h it read 22212220h 22232222h: the pad was the next pixel of the same row.1

Forty-two GP0 stores of a 40-vertex polyline with no wait between them took 531 cycles in the first run and 535 in the run of 28 September 2026. The program counted 54 drawn in the first and 64 in the second.1

CD-ROM With No Disc

Two parameters followed by the invalid command 40h answered INT5 11h 40h. A Getstat after it answered INT5 11h 20h when sent at once and when sent 10,000 or 100,000 cycles later.1

Init answered INT3 then INT2 25,600 cycles later, and Getparam then gave mode 20h. After a Reset (1Ch), a Getstat sent 50,000 to 1,200,000 cycles later got no answer.1

MDEC by DMA After a Reset

Tables sent by DMA0 timed out, and a decode to DMA1 timed out with status A004000Dh. A store of 40000000h to MDEC0 after the reset set the status to B004000Fh.1

With the input full (status E60400DFh) a 33rd word stored by the CPU completed within 31 cycles. The status stayed E60400DFh and no words came out.1

Runs

27 September 2026

00RUN.txt

===== 00 RUN | BIOS 19951204 System ROM Version 3.0 11/18/96 A
12 tests
A chain program, linked at 80100000
Saved on the card in slot 2, from image 1
COP0 at start: BPC 00000000 BDA 00000000 TAR 800160E0 DCIC 00000000 BadVaddr 00000400 BDAM 00000000
BPCM 00000000 SR 00000000 Cause 00000020 EPC 80016C84 PRId 00000002

01FTS.txt

===== 01 FTS FU TIMER2 STOPPED | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 00000400
Timer2 stopped (mode 0001h: sync on, sync mode 0). Each row: the target written, mode
0001h written and read once, the counter written, 500 cycles, then the mode read once.
Bit 11 (0800h) is reached target, bit 12 (1000h) reached FFFFh.
Target 8000, counter written 1234: mode reads 0401, counter reads 1234
Target 8000, counter written 7FFF: mode reads 0401, counter reads 7FFF
Target 8000, counter written 8000: mode reads 0C01, counter reads 8000
Target 8000, counter written 8001: mode reads 0401, counter reads 8001
Target 8000, counter written FFFF: mode reads 0401, counter reads FFFF
Target 8000, counter written 0000: mode reads 0401, counter reads 0000
Target 1234, counter written 1234: mode reads 0C01, counter reads 1234
Target 1234, counter written 1233: mode reads 0401, counter reads 1233
Done.

02FTM.txt

===== 02 FTM FU TIMER MODE READS | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 00000400
Timer0 system clock, mode 0000 written then the counter read at once, 8 times: 0 0 0 0 0 0 0 0
Timer1 system clock, mode 0000 written then the counter read at once, 8 times: 0 0 0 0 0 0 0 0
Timer2 system clock, mode 0000 written then the counter read at once, 8 times: 0 0 0 0 0 0 0 0
Timer1 hblank clock, mode 0100 written then the counter read at once, 8 times: 0 0 0 0 0 0 0 0
Timer0 dotclock, mode 0100 written then the counter read at once, 8 times: 0 0 0 0 0 0 0 0
Done.

03FVB.txt

===== 03 FVB FU T1 VBLANK EDGE | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 00000400
Timer1 sync mode 1 (reset at vblank), set at the vblank IRQ (I_STAT bit 0); timer 2
counts system cycles from then. Where timer 1 first reads lower than before is the reset.
Timer1 system clock, sync mode 1 (mode 0003h):
  Timer1 read 49431 then 22 at 49462 cycles after the vblank IRQ (the read before at 49421)
  Timer1 read 49453 then 31 at 49498 cycles after the vblank IRQ (the read before at 49457)
  Timer1 read 49453 then 29 at 49498 cycles after the vblank IRQ (the read before at 49457)
  Timer1 read 49452 then 29 at 49497 cycles after the vblank IRQ (the read before at 49456)
Timer1 hblank clock, sync mode 1 (mode 0103h):
  Timer1 read 24 then 0 at 52021 cycles after the vblank IRQ (the read before at 51980)
  Timer1 read 24 then 0 at 52044 cycles after the vblank IRQ (the read before at 52003)
  Timer1 read 24 then 0 at 52036 cycles after the vblank IRQ (the read before at 51995)
  Timer1 read 24 then 0 at 52040 cycles after the vblank IRQ (the read before at 51999)
Timer1 hblank clock free run (mode 0100h) zeroed at one vblank IRQ, read at the next: 263 263 263 263
Done.

04FDI.txt

===== 04 FDI FU DICR LATENCY | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 00000400
IRQ3 masked in I_MASK, interrupts off. DICR written, then eight loads of I_STAT, each
followed by a load of timer 2.
DICR 00000000 written; then I_STAT bit 3 and timer 2 (cycles since just before the write): 0@9 0@39 0@66 0@96 0@123 0@153 0@180 0@210
DICR 00008000 written; then I_STAT bit 3 and timer 2 (cycles since just before the write): 0@9 1@39 1@66 1@96 1@126 1@156 1@178 1@208
DICR 00008000 written; then I_STAT bit 3 and timer 2 (cycles since just before the write): 0@9 1@39 1@66 1@102 1@129 1@159 1@181 1@211
DICR 00008000 written; then I_STAT bit 3 and timer 2 (cycles since just before the write): 0@9 1@39 1@69 1@99 1@126 1@156 1@178 1@208
DICR was 00000000 and is back to 0, then its enables.
Done.

05FGT.txt

===== 05 FGT FU GTE IR0 OPCODES | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 00000400
IR0 at the edge (the gteres RTPS inputs, V0 100h,100h,10h, DQA 0):
RTPS sf 1, DQA 0, DQB 1000000: IR0 1000, MAC0 1000000, FLAG 00000000; changed: 8=1000 9=166 10=a1 11=803 14=a000f9 19=803 24=1000000 25=166 26=a1 27=803 28=4022 F=0
RTPS sf 1, DQA 0, DQB 0FFFFFF: IR0 FFF, MAC0 FFFFFF, FLAG 00000000; changed: 8=fff 9=166 10=a1 11=803 14=a000f9 19=803 24=ffffff 25=166 26=a1 27=803 28=4022 F=0
RTPS sf 1, DQA 0, DQB 1000FFF: IR0 1000, MAC0 1000FFF, FLAG 00001000; changed: 8=1000 9=166 10=a1 11=803 14=a000f9 19=803 24=1000fff 25=166 26=a1 27=803 28=4022 F=1000
Every opcode 00h-3Fh with sf 1 and sf 0, lm 0, no other bits, each on the same seeded
inputs as gteres GNA (seed 5501AA00, SXYP IRGB ORGB LZCR not written); the registers
the command changed as <register>=<hex> (0-31 data, 32-63 control), then F=FLAG:
op 00 sf 1: 8=0 9=ffff8000 10=7fff 11=ffff8000 12=1000 14=3fffc00 16=29cd 17=e9f7 18=c3a3 19=0 24=22632822 25=89bcdadc 26=3b542ced 27=80014e52 28=3e0 F=81c7f000
op 00 sf 0: 8=0 9=ffff8000 10=7fff 12=1000 14=3fffc00 16=29cd 17=e9f7 18=c3a3 19=0 24=22632822 25=cdadc000 26=42ced12c 27=14e522f2 F=81c7f000
op 01 sf 1: 8=0 9=ffff8000 10=7fff 11=ffff8000 12=1000 14=3fffc00 16=29cd 17=e9f7 18=c3a3 19=0 24=22632822 25=89bcdadc 26=3b542ced 27=80014e52 28=3e0 F=81c7f000
op 01 sf 0: 8=0 9=ffff8000 10=7fff 12=1000 14=3fffc00 16=29cd 17=e9f7 18=c3a3 19=0 24=22632822 25=cdadc000 26=42ced12c 27=14e522f2 F=81c7f000
op 02 sf 1: 8=0 9=ffff8000 10=7fff 12=1000 14=3fffc00 16=29cd 17=e9f7 18=c3a3 19=0 24=22632822 25=89bcdadc 26=3b542ced F=81c7f000
op 02 sf 0: 8=0 9=ffff8000 10=7fff 12=1000 14=3fffc00 16=29cd 17=e9f7 18=c3a3 19=0 24=22632822 25=cdadc000 26=42ced12c F=81c7f000
op 03 sf 1: 8=0 10=7fff 12=1000 14=3ff03ff 16=29cd 17=e9f7 18=c3a3 19=0 24=22632822 26=3b542ced F=8083f000
op 03 sf 0: 8=0 10=7fff 12=1000 14=3ff03ff 16=29cd 17=e9f7 18=c3a3 19=ffff 24=9b0151c0 26=42ced12c F=80807000
op 04 sf 1: 8=0 12=1000 14=3ffffff 24=9b0151c0 F=80003000
op 04 sf 0: 8=0 12=1000 14=3ffffff 24=9b0151c0 F=80003000
op 05 sf 1: 8=0 9=ffff8000 10=7fff 12=1000 14=3fffc00 16=29cd 17=e9f7 18=c3a3 19=0 24=22632822 25=cdadc000 26=42ced12c 27=14e522f2 F=81c7f000
op 05 sf 0: 8=0 9=ffff8000 10=7fff 12=1000 14=3fffc00 16=29cd 17=e9f7 18=c3a3 19=0 24=22632822 25=cdadc000 26=42ced12c 27=14e522f2 F=81c7f000
op 06 sf 1: 24=0 F=0
op 06 sf 0: 24=0 F=0
op 07 sf 1: 24=a32e6fff F=80008000
op 07 sf 0: 24=e0f76fff F=0
op 08 sf 1: 24=6523efff F=80008000
op 08 sf 0: 24=d3249721 F=0
op 09 sf 1: 24=ac5defff F=0
op 09 sf 0: 24=ac5defff F=0
op 0A sf 1: 24=7d9bb94e F=80008000
op 0A sf 0: 24=eb9c6070 F=0
op 0B sf 1: 8=0 9=ffff8000 10=7fff 12=1000 14=3fffc00 16=29cd 17=e9f7 18=c3a3 19=0 24=22632822 25=cdadc000 26=42ced12c 27=14e522f2 F=81c7f000
op 0B sf 0: 8=0 9=ffff8000 10=7fff 12=1000 14=3fffc00 16=29cd 17=e9f7 18=c3a3 19=0 24=22632822 25=cdadc000 26=42ced12c 27=14e522f2 F=81c7f000
op 0C sf 1: 9=2fcf 10=7fff 11=ffff8001 25=2fcf 26=3fff0 27=ffff8001 28=3ff F=80800000
op 0C sf 0: 9=7fff 10=7fff 11=ffff8000 25=2fcfa06 26=3fff0001 27=f80015fa 28=3ff F=81c00000
op 0D sf 1: 9=ffff8000 10=7fff 11=ffff8001 25=fffa0558 26=3fff0 27=ffff8001 28=3e0 F=81800000
op 0D sf 0: 9=ffff8000 10=7fff 11=ffff8000 25=8ecd0fff 26=3fff0001 27=f80015fa 28=3e0 F=81c00000
op 0E sf 1: 10=7fff 11=ffff8000 26=3ffe8 27=fffdabf1 28=3e0 F=80c00000
op 0E sf 0: 10=ffff8000 26=bffe0001 27=6afc15f9 28=7c00 F=80c00000
op 0F sf 1: 8=0 9=ffff8000 10=7fff 12=1000 14=3fffc00 16=29cd 17=e9f7 18=c3a3 19=0 24=22632822 25=cdadc000 26=42ced12c 27=14e522f2 F=81c7f000
op 0F sf 0: 8=0 9=ffff8000 10=7fff 12=1000 14=3fffc00 16=29cd 17=e9f7 18=c3a3 19=0 24=22632822 25=cdadc000 26=42ced12c 27=14e522f2 F=81c7f000
op 10 sf 1: 10=7fff 11=0 20=b3b04688 21=1000 22=7f00ff00 25=ffffffff 26=87ef 27=0 28=3e0 F=80b00000
op 10 sf 0: 9=ffff8000 10=7fff 11=ffff8000 20=b3b04688 21=1000 22=7f00ff00 25=f8ff0000 26=87ef000 27=f8ff0000 28=3e0 F=81f80000
op 11 sf 1: 10=7fff 11=0 20=b3b04688 21=1000 22=7f00ff00 25=ffffffff 26=8fff 27=0 28=3e0 F=80b00000
op 11 sf 0: 9=fffff000 10=7fff 11=fffff000 20=b3b04688 21=1000 22=7f00ff00 25=fffff000 26=8fff000 27=fffff000 28=3e0 F=80f80000
op 12 sf 1: 9=ffff8000 10=7fff 11=ffff8000 25=89bcdadc 26=3b542ced 27=80014e52 28=3e0 F=81c00000
op 12 sf 0: 9=ffff8000 10=7fff 25=cdadc000 26=42ced12c 27=14e522f2 F=81c00000
op 13 sf 1: 9=fffffffe 10=407f 11=0 20=b3b04688 21=1000 22=7f00ff00 25=fffffffe 26=407f 27=0 28=3e0 F=89f00000
op 13 sf 0: 9=ffff8000 10=7fff 11=ffff8000 20=b3b04688 21=1000 22=7f00ff00 25=fff7f010 26=bf7e810 27=fff7f010 28=3e0 F=c9f80000
op 14 sf 1: 10=407f 11=0 20=b3b04688 21=1000 22=7f00ff00 25=ffffffff 26=407f 27=0 28=3e0 F=81f00000
op 14 sf 0: 9=ffff8000 10=7fff 11=ffff8000 20=b3b04688 21=1000 22=7f00ff00 25=fff7f010 26=bf7e810 27=fff7f010 28=3e0 F=81f80000
op 15 sf 1: 9=fffffffe 10=7fff 11=ffffffff 20=b3b04688 21=1000 22=7f00ff00 25=fffffffe 26=bf7e 27=ffffffff 28=3e0 F=80b80000
op 15 sf 0: 9=ffff8000 10=7fff 11=ffff8000 20=b3b04688 21=1000 22=7f00ff00 25=fff7f010 26=bf7e810 27=fff7f010 28=3e0 F=81f80000
op 16 sf 1: 9=fffffffe 10=407f 11=0 20=7f00ff00 21=7f00ff00 22=7f00ff00 25=fffffffe 26=407f 27=0 28=3e0 F=89f00000
op 16 sf 0: 9=ffff8000 10=7fff 11=ffff8000 20=7f00ff00 21=7f00ff00 22=7f00ff00 25=fff7f010 26=bf7e810 27=fff7f010 28=3e0 F=c9f80000
op 17 sf 1: 10=407f 11=0 20=7f00ff00 21=7f00ff00 22=7f00ff00 25=ffffffff 26=407f 27=0 28=3e0 F=89f00000
op 17 sf 0: 9=ffff8000 10=7fff 11=ffff8000 20=7fffff00 21=7fffff00 22=7f00ff00 25=fff7f010 26=bf7e810 27=fff7f010 28=3e0 F=c9f80000
op 18 sf 1: 9=fffffffe 10=7fff 11=ffffffff 20=7f00ff00 21=7f00ff00 22=7f00ff00 25=fffffffe 26=87ef 27=ffffffff 28=3e0 F=80b80000
op 18 sf 0: 9=ffff8000 10=7fff 11=ffff8000 20=7fffff00 21=7fffff00 22=7f00ff00 25=fffef010 26=87ef000 27=fff7f010 28=3e0 F=81f80000
op 19 sf 1: 9=fffffffe 10=7fff 11=ffffffff 20=1000 21=7f00ff00 22=7f00ff00 25=fffffffe 26=87ef 27=ffffffff 28=3e0 F=80b80000
op 19 sf 0: 9=ffff8000 10=7fff 11=ffff8000 20=1000 21=7fffff00 22=7f00ff00 25=fffef010 26=87ef000 27=fff7f010 28=3e0 F=81f80000
op 1A sf 1: 9=fffffffe 10=7fff 11=ffffffff 20=b3b04688 21=1000 22=7f00ff00 25=fffffffe 26=87ef 27=ffffffff 28=3e0 F=80b80000
op 1A sf 0: 9=ffff8000 10=7fff 11=ffff8000 20=b3b04688 21=1000 22=7f00ff00 25=fffef010 26=87ef000 27=fff7f010 28=3e0 F=81f80000
op 1B sf 1: 9=7f7f 10=ffffc080 11=ffff8080 20=b3b04688 21=1000 22=7f0000ff 25=7f7f 26=ffffc080 27=ffff8080 28=1f F=89f80000
op 1B sf 0: 9=7fff 10=7fff 20=b3b04688 21=1000 22=7fffffff 25=7f7f010 26=3f7f810 27=7f7f010 28=7fff F=c9f80000
op 1C sf 1: 9=ffff8080 10=ffffc080 11=ffff8080 20=b3b04688 21=1000 22=7f000000 25=ffff8080 26=ffffc080 27=ffff8080 28=0 F=81f80000
op 1C sf 0: 9=7fff 10=7fff 20=b3b04688 21=1000 22=7fffffff 25=7f7f010 26=3f7f810 27=7f7f010 28=7fff F=81f80000
op 1D sf 1: 9=7f7f 10=3f7f 11=7f7f 20=b3b04688 21=1000 22=7fffffff 25=7f7f 26=3f7f 27=7f7f 28=7fff F=380000
op 1D sf 0: 9=7fff 10=7fff 20=b3b04688 21=1000 22=7fffffff 25=7f7f010 26=3f7f810 27=7f7f010 28=7fff F=81f80000
op 1E sf 1: 9=7fff 10=ffff8000 11=ffff8000 20=b3b04688 21=1000 22=7f0000ff 25=7fffbc38 26=c6c54f47 27=91147f57 28=1f F=89f80000
op 1E sf 0: 9=7fff 10=7fff 20=b3b04688 21=1000 22=7fffffff 25=8008000 26=54f42001 27=11c8cc8d 28=7fff F=c9f80000
op 1F sf 1: 9=ffff8000 10=ffff8000 11=ffff8000 20=b3b04688 21=1000 22=7f000000 25=80008008 26=c6c54f42 27=91111c8c 28=0 F=c9f80000
op 1F sf 0: 9=7fff 10=7fff 20=b3b04688 21=1000 22=7fffffff 25=8008000 26=54f42001 27=11c8cc8d 28=7fff F=c9f80000
op 20 sf 1: 9=7fff 10=ffff8000 11=ffff8000 20=7f0000ff 21=7f0000ff 22=7f0000ff 25=7ffd9240 26=c6c54f44 27=9115b687 28=1f F=89f80000
op 20 sf 0: 9=7fff 10=7fff 20=7fffffff 21=7fffffff 22=7fffffff 25=8008000 26=54f42001 27=11c8cc8d 28=7fff F=c9f80000
op 21 sf 1: 9=ffff8000 10=ffff8000 11=ffff8000 20=7f000000 21=7f000000 22=7f000000 25=80000008 26=c6c54f39 27=9111a48f 28=0 F=c9f80000
op 21 sf 0: 9=7fff 10=7fff 20=7fffffff 21=7fffffff 22=7fffffff 25=8000 26=54f39001 27=1a48fc8d 28=7fff F=c9f80000
op 22 sf 1: 9=ffff8000 10=ffff8000 11=ffff8000 20=7f0000ff 21=7f000000 22=7f000000 25=80000008 26=c6c54f39 27=9111a48f 28=0 F=c9f80000
op 22 sf 0: 9=7fff 10=7fff 20=7fffff00 21=7fffffff 22=7fffffff 25=8000 26=54f39001 27=1a48fc8d 28=7fff F=c9f80000
op 23 sf 1: 9=ffff8000 10=ffff8000 11=ffff8000 20=7f002311 21=7f000000 22=7f000000 25=80000008 26=c6c54f39 27=9111a48f 28=0 F=c9f80000
op 23 sf 0: 9=7fff 10=7fff 20=7fff2311 21=7fffffff 22=7fffffff 25=8000 26=54f39001 27=1a48fc8d 28=7fff F=c9f80000
op 24 sf 1: 9=ffff8000 10=ffff8000 11=ffff8000 20=1000 21=7f000000 22=7f000000 25=80000008 26=c6c54f39 27=9111a48f 28=0 F=c9f80000
op 24 sf 0: 9=7fff 10=7fff 20=1000 21=7fffffff 22=7fffffff 25=8000 26=54f39001 27=1a48fc8d 28=7fff F=c9f80000
op 25 sf 1: 9=ffff8000 10=ffff8000 11=ffff8000 20=b3b04688 21=1000 22=7f000000 25=80000008 26=c6c54f39 27=9111a48f 28=0 F=81f80000
op 25 sf 0: 9=7fff 10=7fff 20=b3b04688 21=1000 22=7fffffff 25=8000 26=54f39001 27=1a48fc8d 28=7fff F=81f80000
op 26 sf 1: 10=ffff8000 11=ffff8000 20=b3b04688 21=1000 22=7f0000ff 26=c6c54f39 27=9111a48f 28=0 F=80d80000
op 26 sf 0: 10=7fff 20=b3b04688 21=1000 22=7fffffff 26=54f39001 27=1a48fc8d F=80d80000
op 27 sf 1: 11=ffff8000 20=b3b04688 21=1000 22=7f002311 27=9111a48f 28=3e0 F=480000
op 27 sf 0: 20=b3b04688 21=1000 22=7fff2311 27=1a48fc8d F=480000
op 28 sf 1: 9=0 25=0 26=1000 27=3fff0 F=400000
op 28 sf 0: 9=1 10=7fff 25=1 26=1000000 27=3fff0001 F=80c00000
op 29 sf 1: 9=fffffffe 10=7fff 11=ffffffff 20=b3b04688 21=1000 22=7f00ff00 25=fffffffe 26=87ef 27=ffffffff 28=3e0 F=80b80000
op 29 sf 0: 9=ffff8000 10=7fff 11=ffff8000 20=b3b04688 21=1000 22=7f00ff00 25=fffef010 26=87ef000 27=fff7f010 28=3e0 F=81f80000
op 2A sf 1: 10=7fff 11=0 20=7f00ff00 21=7f00ff00 22=7f00ff00 25=ffffffff 26=80ff 27=0 28=3e0 F=80b00000
op 2A sf 0: 9=ffff8000 10=7fff 11=0 20=7f00ff00 21=7f00ff00 22=7f00ff00 25=ff000000 26=80ff000 27=0 28=3e0 F=81f80000
op 2B sf 1: 10=7fff 11=0 20=7f00ff00 22=7f00ff00 25=ffffffff 26=80ff 27=0 28=3e0 F=80b00000
op 2B sf 0: 9=ffff8000 10=7fff 11=0 20=7f00ff00 22=7f00ff00 25=ff000000 26=80ff000 27=0 28=3e0 F=81f80000
op 2C sf 1: 20=7f00ff00 F=80b00000
op 2C sf 0: 20=7f00ff00 F=81f80000
op 2D sf 1: 7=0 24=ef21e181 F=80040000
op 2D sf 0: 7=0 24=ef21e181 F=80040000
op 2E sf 1: 7=0 24=c57ae939 F=80040000
op 2E sf 0: 7=0 24=c57ae939 F=80040000
op 2F sf 1: 7=0 8=0 9=ffff8000 10=7fff 12=1000 14=3fffc00 16=29cd 17=e9f7 18=c3a3 19=0 24=22632822 25=cdadc000 26=42ced12c 27=14e522f2 F=81c7f000
op 2F sf 0: 7=0 8=0 9=ffff8000 10=7fff 12=1000 14=3fffc00 16=29cd 17=e9f7 18=c3a3 19=0 24=22632822 25=cdadc000 26=42ced12c 27=14e522f2 F=81c7f000
op 30 sf 1: 8=0 9=ffff8000 10=7fff 11=ffff8000 12=3fffc00 13=3fffc00 14=3fffc00 16=c3a3 17=0 18=0 19=0 24=22632822 25=89c65e89 26=3b532619 27=8000c44b 28=3e0 F=81c7f000
op 30 sf 0: 8=0 9=7fff 10=7fff 12=3fffc00 13=3ff03ff 14=3ff03ff 16=c3a3 17=0 18=0 19=0 24=22632822 25=65e89000 26=32619148 27=c44b20b 28=7fff F=81c7f000
op 31 sf 1: 8=0 9=ffff8000 10=7fff 11=ffff8000 12=3fffc00 13=3fffc00 14=3fffc00 16=c3a3 17=0 18=0 19=0 24=22632822 25=89c65e89 26=3b532619 27=8000c44b 28=3e0 F=81c7f000
op 31 sf 0: 8=0 9=7fff 10=7fff 12=3fffc00 13=3ff03ff 14=3ff03ff 16=c3a3 17=0 18=0 19=0 24=22632822 25=65e89000 26=32619148 27=c44b20b 28=7fff F=81c7f000
op 32 sf 1: 8=0 9=ffff8000 10=7fff 11=ffff8000 12=3fffc00 13=3fffc00 14=3fffc00 16=c3a3 17=0 18=0 19=0 24=22632822 25=89c65e89 26=3b532619 27=8000c44b 28=3e0 F=81c7f000
op 32 sf 0: 8=0 9=7fff 10=7fff 12=3fffc00 13=3ff03ff 14=3ff03ff 16=c3a3 17=0 18=0 19=0 24=22632822 25=65e89000 26=32619148 27=c44b20b 28=7fff F=81c7f000
op 33 sf 1: 8=0 9=ffff8000 10=7fff 11=ffff8000 12=3fffc00 13=3fffc00 14=3fffc00 16=c3a3 17=0 18=0 19=0 24=22632822 25=89c65e89 26=3b532619 27=8000c44b 28=3e0 F=81c7f000
op 33 sf 0: 8=0 9=7fff 10=7fff 12=3fffc00 13=3ff03ff 14=3ff03ff 16=c3a3 17=0 18=0 19=0 24=22632822 25=65e89000 26=32619148 27=c44b20b 28=7fff F=81c7f000
op 34 sf 1: 8=0 9=ffff8000 10=7fff 11=ffff8000 12=3fffc00 13=3fffc00 14=3fffc00 16=e9f7 17=c3a3 18=0 19=0 24=22632822 25=89c65e89 26=3b532619 27=8000c44b 28=3e0 F=81c7f000
op 34 sf 0: 8=0 9=7fff 10=7fff 12=3fffc00 13=3ff03ff 14=3ff03ff 16=e9f7 17=c3a3 18=0 19=0 24=22632822 25=65e89000 26=32619148 27=c44b20b 28=7fff F=81c7f000
op 35 sf 1: 8=0 9=ffff8000 10=7fff 12=3fffc00 13=3fffc00 14=3ffff99 16=e9f7 17=c3a3 18=0 19=ffff 24=9b0151c0 25=89c65e89 26=3b532619 F=81c7f000
op 35 sf 0: 8=0 9=7fff 10=7fff 12=3ffff99 13=3ff03ff 14=3ff03ff 16=e9f7 17=c3a3 18=0 19=ffff 24=9b0151c0 25=65e89000 26=32619148 28=7fff F=81c77000
op 36 sf 1: 8=0 9=ffff8000 10=7fff 12=3ffff99 13=3ff03ff 14=3fffc00 16=29cd 17=e9f7 18=c3a3 19=0 24=22632822 25=89c65e89 26=3b532619 F=8183f000
op 36 sf 0: 8=0 9=7fff 10=7fff 12=3fffc00 13=3ff03ff 14=3ff03ff 16=29cd 17=e9f7 18=c3a3 19=0 24=22632822 25=65e89000 26=32619148 28=7fff F=8183f000
op 37 sf 1: 8=0 10=7fff 12=3fffc00 13=3ff03ff 14=3ff03ff 16=29cd 17=e9f7 18=c3a3 19=0 24=22632822 26=3b532619 F=8083f000
op 37 sf 0: 8=0 10=7fff 12=3fffc00 13=3ff03ff 14=3ff03ff 16=29cd 17=e9f7 18=c3a3 19=0 24=22632822 26=32619148 F=8083f000
op 38 sf 1: 8=0 10=7fff 12=3fffc00 13=3ff03ff 14=3ff03ff 16=29cd 17=e9f7 18=c3a3 19=0 24=22632822 26=3b532619 F=8083f000
op 38 sf 0: 8=0 10=7fff 12=3fffc00 13=3ff03ff 14=3ff03ff 16=29cd 17=e9f7 18=c3a3 19=0 24=22632822 26=32619148 F=8083f000
op 39 sf 1: 8=0 12=3fffc00 13=3ff03ff 14=3fffffe 16=29cd 17=e9f7 18=c3a3 19=0 24=22632822 F=8001f000
op 39 sf 0: 8=0 12=3fffc00 13=3ff03ff 14=3fffffe 16=29cd 17=e9f7 18=c3a3 19=0 24=22632822 F=8001f000
op 3A sf 1: 8=0 12=1000 13=3ff03ff 14=3fffffe 16=29cd 17=e9f7 18=c3a3 19=0 24=22632822 F=8001f000
op 3A sf 0: 8=0 12=1000 13=3ff03ff 14=3fffffe 16=29cd 17=e9f7 18=c3a3 19=0 24=22632822 F=8001f000
op 3B sf 1: 8=0 12=1000 14=3fffffe 24=22632822 F=8000b000
op 3B sf 0: 8=0 12=1000 14=3fffffe 24=22632822 F=8000b000
op 3C sf 1: 8=0 9=ffff8000 10=7fff 12=1000 14=3fffc00 16=29cd 17=e9f7 18=c3a3 19=0 24=22632822 25=cdadc000 26=42ced12c 27=14e522f2 F=81c7f000
op 3C sf 0: 8=0 9=ffff8000 10=7fff 12=1000 14=3fffc00 16=29cd 17=e9f7 18=c3a3 19=0 24=22632822 25=cdadc000 26=42ced12c 27=14e522f2 F=81c7f000
op 3D sf 1: 20=b3b04688 21=1000 22=7fffff00 25=ffffffff 26=1000 27=7fff F=380000
op 3D sf 0: 9=fffff000 10=7fff 20=b3b04688 21=1000 22=7fffff00 25=fffff000 26=1000000 27=7fff000 F=80f80000
op 3E sf 1: 9=7fff 10=ffff8000 20=b3b04688 21=1000 22=7fff00ff 25=53157f31 26=db67a9fc 27=43e637f3 28=7c1f F=81f80000
op 3E sf 0: 9=7fff 10=ffff8000 20=b3b04688 21=1000 22=7fff00ff 25=53156f32 26=dc6799fc 27=4be5a7f4 28=7c1f F=81f80000
op 3F sf 1: 9=7f7f 10=ffffc080 11=ffff8080 20=7f0000ff 21=7f0000ff 22=7f0000ff 25=7f7f 26=ffffc080 27=ffff8080 28=1f F=89f80000
op 3F sf 0: 9=7fff 10=7fff 20=7fffffff 21=7fffffff 22=7fffffff 25=7f7f010 26=3f7f810 27=7f7f010 28=7fff F=c9f80000
Done.

06FMD.txt

===== 06 FMD FU MDEC RESET COLOUR | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 00000400
Reset timing: MDEC1 written 80000000h, then MDEC1 read eight times, each followed by
a timer 2 read (cycles since just before the write).
Idle, status after the reset write @ timer 2: 80040000@14 80040000@43 80040000@65 80040000@83 80040000@101 80040000@119 80040000@137 80040000@155
15 bit decode with the input full, nothing read, status after the reset write @ timer 2: E60400DF@14 80040000@43 80040000@61 80040000@79 80040000@97 80040000@115 80040000@133 80040000@151
Short decode counts by CPU (mdecout ODD's way): the 4bit/8bit block at 8 bit with its
tables, the step stream at 15 bit with its tables. Only `count` words are written.
8 bit, decode count 1, 1 words written: 48 words out, CRC A9DEB035, status 8204FFFF, first 8F9EA9AF last 118AFF72
8 bit, decode count 2, 2 words written: 32 words out, CRC F60B4B13, status 8204FFFF, first FFFB7B20 last 118AFF72
15 bit, decode count 4, 4 words written: 32 words out, CRC C2A8FA9D, status 8601FFFF, first 00000000 last 00000000
15 bit, decode count 5, 5 words written: 32 words out, CRC C2A8FA9D, status 8601FFFF, first 00000000 last 00000000
15 bit, decode count 6, 6 words written: 32 words out, CRC C2A8FA9D, status 8601FFFF, first 00000000 last 00000000
Colour matrix and clamp: one macroblock of DC-only blocks, Cr and Cb and all four Y as
given (10 bit DC values), quant table all 4, the standard scale table, unsigned, by CPU.
The first output word of each 8x8 quadrant at 24 bit and at 15 bit.
Cr -256 Cb -256 Y 0: 24 bit 192 words, 0000FF00 0000FF00 0000FF00 0000FF00; 15 bit 128 words, 03E003E0 03E003E0 03E003E0 03E003E0
Cr -256 Cb -64 Y 0: 24 bit 192 words, 0047E700 0047E700 0047E700 0047E700; 15 bit 128 words, 27A027A0 27A027A0 27A027A0 27A027A0
Cr -256 Cb 0 Y 0: 24 bit 192 words, 0080DC00 0080DC00 0080DC00 0080DC00; 15 bit 128 words, 43604360 43604360 43604360 43604360
Cr -256 Cb 64 Y 0: 24 bit 192 words, 00B9D100 00B9D100 00B9D100 00B9D100; 15 bit 128 words, 5F405F40 5F405F40 5F405F40 5F405F40
Cr -256 Cb 255 Y 0: 24 bit 192 words, 00FFB000 00FFB000 00FFB000 00FFB000; 15 bit 128 words, 7EC07EC0 7EC07EC0 7EC07EC0 7EC07EC0
Cr -64 Cb -256 Y 0: 24 bit 192 words, 5300C353 5300C353 5300C353 5300C353; 15 bit 128 words, 030A030A 030A030A 030A030A 030A030A
Cr -64 Cb -64 Y 0: 24 bit 192 words, 5347A253 5347A253 5347A253 5347A253; 15 bit 128 words, 268A268A 268A268A 268A268A 268A268A
Cr -64 Cb 0 Y 0: 24 bit 192 words, 53809753 53809753 53809753 53809753; 15 bit 128 words, 426A426A 426A426A 426A426A 426A426A
Cr -64 Cb 64 Y 0: 24 bit 192 words, 53B98C53 53B98C53 53B98C53 53B98C53; 15 bit 128 words, 5E2A5E2A 5E2A5E2A 5E2A5E2A 5E2A5E2A
Cr -64 Cb 255 Y 0: 24 bit 192 words, 53FF6B53 53FF6B53 53FF6B53 53FF6B53; 15 bit 128 words, 7DAA7DAA 7DAA7DAA 7DAA7DAA 7DAA7DAA
Cr 0 Cb -256 Y 0: 24 bit 192 words, 8000AC80 8000AC80 8000AC80 8000AC80; 15 bit 128 words, 02D002D0 02D002D0 02D002D0 02D002D0
Cr 0 Cb -64 Y 0: 24 bit 192 words, 80478B80 80478B80 80478B80 80478B80; 15 bit 128 words, 26302630 26302630 26302630 26302630
Cr 0 Cb 0 Y 0: 24 bit 192 words, 80808080 80808080 80808080 80808080; 15 bit 128 words, 42104210 42104210 42104210 42104210
Cr 0 Cb 64 Y 0: 24 bit 192 words, 80B97580 80B97580 80B97580 80B97580; 15 bit 128 words, 5DF05DF0 5DF05DF0 5DF05DF0 5DF05DF0
Cr 0 Cb 255 Y 0: 24 bit 192 words, 80FF5480 80FF5480 80FF5480 80FF5480; 15 bit 128 words, 7D707D70 7D707D70 7D707D70 7D707D70
Cr 64 Cb -256 Y 0: 24 bit 192 words, AD0095AD AD0095AD AD0095AD AD0095AD; 15 bit 128 words, 02760276 02760276 02760276 02760276
Cr 64 Cb -64 Y 0: 24 bit 192 words, AD4774AD AD4774AD AD4774AD AD4774AD; 15 bit 128 words, 25F625F6 25F625F6 25F625F6 25F625F6
Cr 64 Cb 0 Y 0: 24 bit 192 words, AD8069AD AD8069AD AD8069AD AD8069AD; 15 bit 128 words, 41B641B6 41B641B6 41B641B6 41B641B6
Cr 64 Cb 64 Y 0: 24 bit 192 words, ADB95EAD ADB95EAD ADB95EAD ADB95EAD; 15 bit 128 words, 5D965D96 5D965D96 5D965D96 5D965D96
Cr 64 Cb 255 Y 0: 24 bit 192 words, ADFF3DAD ADFF3DAD ADFF3DAD ADFF3DAD; 15 bit 128 words, 7D167D16 7D167D16 7D167D16 7D167D16
Cr 255 Cb -256 Y 0: 24 bit 192 words, FF0051FF FF0051FF FF0051FF FF0051FF; 15 bit 128 words, 015F015F 015F015F 015F015F 015F015F
Cr 255 Cb -64 Y 0: 24 bit 192 words, FF4730FF FF4730FF FF4730FF FF4730FF; 15 bit 128 words, 24DF24DF 24DF24DF 24DF24DF 24DF24DF
Cr 255 Cb 0 Y 0: 24 bit 192 words, FF8025FF FF8025FF FF8025FF FF8025FF; 15 bit 128 words, 40BF40BF 40BF40BF 40BF40BF 40BF40BF
Cr 255 Cb 64 Y 0: 24 bit 192 words, FFB91AFF FFB91AFF FFB91AFF FFB91AFF; 15 bit 128 words, 5C7F5C7F 5C7F5C7F 5C7F5C7F 5C7F5C7F
Cr 255 Cb 255 Y 0: 24 bit 192 words, FFFF00FF FFFF00FF FFFF00FF FFFF00FF; 15 bit 128 words, 7C1F7C1F 7C1F7C1F 7C1F7C1F 7C1F7C1F
Cr -256 Cb -256 Y -128: 24 bit 192 words, 00FFC800 00FFC800 00FFC800 00FFC800; 15 bit 128 words, 7F207F20 7F207F20 7F207F20 7F207F20
Cr -256 Cb -256 Y 127: 24 bit 192 words, 0C00FF0C 0C00FF0C 0C00FF0C 0C00FF0C; 15 bit 128 words, 03E103E1 03E103E1 03E103E1 03E103E1
Cr -256 Cb 255 Y -128: 24 bit 192 words, 00FF7000 00FF7000 00FF7000 00FF7000; 15 bit 128 words, 7DC07DC0 7DC07DC0 7DC07DC0 7DC07DC0
Cr -256 Cb 255 Y 127: 24 bit 192 words, 0C00EF0C 0C00EF0C 0C00EF0C 0C00EF0C; 15 bit 128 words, 03C103C1 03C103C1 03C103C1 03C103C1
Cr 255 Cb -256 Y -128: 24 bit 192 words, F2FF11F2 F2FF11F2 F2FF11F2 F2FF11F2; 15 bit 128 words, 7C5E7C5E 7C5E7C5E 7C5E7C5E 7C5E7C5E
Cr 255 Cb -256 Y 127: 24 bit 192 words, FF0090FF FF0090FF FF0090FF FF0090FF; 15 bit 128 words, 025F025F 025F025F 025F025F 025F025F
Cr 255 Cb 255 Y -128: 24 bit 192 words, F2FF00F2 F2FF00F2 F2FF00F2 F2FF00F2; 15 bit 128 words, 7C1E7C1E 7C1E7C1E 7C1E7C1E 7C1E7C1E
Cr 255 Cb 255 Y 127: 24 bit 192 words, FF0038FF FF0038FF FF0038FF FF0038FF; 15 bit 128 words, 00FF00FF 00FF00FF 00FF00FF 00FF00FF
Cr 0 Cb 0 Y -128: 24 bit 192 words, 40404040 40404040 40404040 40404040; 15 bit 128 words, 21082108 21082108 21082108 21082108
Cr 0 Cb 0 Y 127: 24 bit 192 words, BFBFBFBF BFBFBFBF BFBFBFBF BFBFBFBF; 15 bit 128 words, 63186318 63186318 63186318 63186318
Cr 64 Cb -64 Y -128: 24 bit 192 words, 6D07346D 6D07346D 6D07346D 6D07346D; 15 bit 128 words, 04EE04EE 04EE04EE 04EE04EE 04EE04EE
Cr 64 Cb -64 Y 127: 24 bit 192 words, EC86B3EC EC86B3EC EC86B3EC EC86B3EC; 15 bit 128 words, 46DD46DD 46DD46DD 46DD46DD 46DD46DD
Cr -64 Cb 64 Y -128: 24 bit 192 words, 13794C13 13794C13 13794C13 13794C13; 15 bit 128 words, 3D223D22 3D223D22 3D223D22 3D223D22
Cr -64 Cb 64 Y 127: 24 bit 192 words, 92F8CB92 92F8CB92 92F8CB92 92F8CB92; 15 bit 128 words, 7F327F32 7F327F32 7F327F32 7F327F32
Done.

07FSP.txt

===== 07 FSP FU SPU ENV FIFO | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 00000400
Envelope counter, one for all voices or one each: voices 0 and 1 attack linear shift
16 step 0, keyed on 1500 cycles apart; cycles from voice 0's KON.
Voice 0 keyed on at 0, voice 1 at 1645; first level changes, voice 0: 8029 32589 57229 81797; voice 1: 8029 32589 57229 81797; levels then 002A 002A
Voice 0 keyed on at 0, voice 1 at 1602; first level changes, voice 0: 17900 42452 67011 91564; voice 1: 17900 42452 67011 91564; levels then 002A 002A
Voice 0 keyed on at 0, voice 1 at 1602; first level changes, voice 0: 17900 42452 67011 91564; voice 1: 17900 42452 67011 91564; levels then 002A 002A
ADSR level times the sample: tone T on voice 1, pitch 1000h, held at 7FFFh; the level
register written, then the voice 1 capture buffer (first 16 samples).
Level as it stands, 255 changes in 256:
  FD4A FF98 007E 00FE 017D 01FD 027C 02FC 024B FD30 FC83 FD03 FD82 FE01 FE81 FF00
Level read 3FFF
Level written 4000h, reads 4000
Level 4000h, 255 changes in 256:
  024C FD30 FC83 FD03 FD82 FE01 FE81 FF00 FF80 FFFF 007F 00FE 017E 01FD 027D 02FC
Level written 7FFFh, reads 7FFF
Level 7FFFh, 255 changes in 256:
  FF00 FFFF 00FD 01FC 02FB 03FA 04F9 05F8 0497 FA60 F907 FA06 FB11 FC50 FD8A FEAF
FIFO drain: halfwords B000h, B001h, .. to scratch at 30000h (filled EEEEh) by one DMA
block of 16 words, a wait, SPUCNT transfer mode Stop, then read back by DMA.
Wait 0 cycles after the DMA ended: 8 of 32 halfwords written, 0 still EEEEh, first B000 last 5555
Wait 100 cycles after the DMA ended: 9 of 32 halfwords written, 0 still EEEEh, first B000 last 5555
Wait 200 cycles after the DMA ended: 10 of 32 halfwords written, 0 still EEEEh, first B000 last 5555
Wait 300 cycles after the DMA ended: 14 of 32 halfwords written, 0 still EEEEh, first B000 last 5555
Wait 400 cycles after the DMA ended: 18 of 32 halfwords written, 0 still EEEEh, first B000 last 5555
Wait 500 cycles after the DMA ended: 22 of 32 halfwords written, 0 still EEEEh, first B000 last 5555
Wait 600 cycles after the DMA ended: 26 of 32 halfwords written, 0 still EEEEh, first B000 last 5555
Wait 700 cycles after the DMA ended: 30 of 32 halfwords written, 0 still EEEEh, first B000 last 5555
Wait 800 cycles after the DMA ended: 32 of 32 halfwords written, 0 still EEEEh, first B000 last B01F
Wait 900 cycles after the DMA ended: 32 of 32 halfwords written, 0 still EEEEh, first B000 last B01F
Wait 1000 cycles after the DMA ended: 32 of 32 halfwords written, 0 still EEEEh, first B000 last B01F
Wait 1100 cycles after the DMA ended: 32 of 32 halfwords written, 0 still EEEEh, first B000 last B01F
Wait 1200 cycles after the DMA ended: 32 of 32 halfwords written, 0 still EEEEh, first B000 last B01F
Wait 1300 cycles after the DMA ended: 32 of 32 halfwords written, 0 still EEEEh, first B000 last B01F
Wait 1400 cycles after the DMA ended: 32 of 32 halfwords written, 0 still EEEEh, first B000 last B01F
Wait 1500 cycles after the DMA ended: 32 of 32 halfwords written, 0 still EEEEh, first B000 last B01F
Wait 1600 cycles after the DMA ended: 32 of 32 halfwords written, 0 still EEEEh, first B000 last B01F
Start address one 8 byte unit past a block (spuenv END's S4+8 case): tone T on voice 1,
pitch 1000h, start and repeat as given; the voice 1 capture buffer.
Start 40C0h (the block), 66 changes in 256:
  0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
  0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
Start 40C1h (one unit in), 255 changes in 256:
  FE29 FDC7 FD6A FD14 FD4A FF98 007E 00FE 017D 01FD 027C 02FC 024B FD30 FC83 FD03
  FD82 FE01 FE81 FF00 FF80 FFFF 007E 00FE 017D 01FD 027C 02FC 024B FD30 FC83 FD03
Done.

08FDS.txt

===== 08 FDS FU DMA SPU BLOCKS | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 00000400
DMA4 SPU write SyncMode 1, 256 words to 30000h, cycles from the CHCR write until bit 24
clears, three times each. SPU delay register (1F801014h) was 200931E1.
Delay 200931E1, blocks of 1 words x 256: 16343 16331 16327
Delay 200931E1, blocks of 2 words x 128: 16312 16281 16278
Delay 200931E1, blocks of 4 words x 64: 18283 18282 18282
Delay 200931E1, blocks of 8 words x 32: 17029 17028 17028
Delay 200931E1, blocks of 16 words x 16: 16846 16795 16795
Delay 200931E1, blocks of 32 words x 8: 8515 8522 8522
Delay 210931E1, blocks of 1 words x 256: 16350 16338 16368
Delay 210931E1, blocks of 2 words x 128: 17236 17272 17272
Delay 210931E1, blocks of 4 words x 64: 18317 18281 18281
Delay 210931E1, blocks of 8 words x 32: 17927 17887 17927
Delay 210931E1, blocks of 16 words x 16: 17544 17266 17266
Delay 210931E1, blocks of 32 words x 8: 8621 8575 8582
Delay 220931E1, blocks of 1 words x 256: 16368 16384 16384
Delay 220931E1, blocks of 2 words x 128: 19534 19575 19575
Delay 220931E1, blocks of 4 words x 64: 18325 18329 18329
Delay 220931E1, blocks of 8 words x 32: 18631 18644 18621
Delay 220931E1, blocks of 16 words x 16: 17759 17748 17748
Delay 220931E1, blocks of 32 words x 8: 9488 9464 9464
Delay 230931E1, blocks of 1 words x 256: 16376 16385 16385
Delay 230931E1, blocks of 2 words x 128: 19592 19572 19572
Delay 230931E1, blocks of 4 words x 64: 19441 19457 19457
Delay 230931E1, blocks of 8 words x 32: 18699 18663 18663
Delay 230931E1, blocks of 16 words x 16: 17819 17808 17808
Delay 230931E1, blocks of 32 words x 8: 10196 10165 10165
SPU delay register back to 200931E1
Done.

09FSI.txt

===== 09 FSI FU SIO RXEN IMASK | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 00000400
Controller port with RXEN and no device selected (JOY_CTRL bit 1 clear), slot 1.
CTRL 0004, no data written; JOY_STAT (bits 0-10) every 100 cycles from 0 to 3000:
  005 005 005 005 005 005 005 005 005 005 005 005 005 007 007 007 007 007 007 007 007 007 007 007 007 007 007 007 007 007 007
  bytes in the RX FIFO: 1 FF; I_STAT bit 7 then 0
CTRL 0805, no data written; JOY_STAT (bits 0-10) every 100 cycles from 0 to 3000:
  005 005 005 005 005 005 005 005 005 005 005 005 005 005 207 207 207 207 207 207 207 207 207 207 207 207 207 207 207 207 207
  bytes in the RX FIFO: 1 FF; I_STAT bit 7 then 1
I_MASK's upper half (the console read 960507FFh after sw FFFFFFFFh, chainb/028/01IMR.txt:4):
sw 12345678h to I_MASK, lw at once: AD090678
sw 12345678h, lui/ori of CAFEBABEh, then lw: AD090678
sw 12345678h, lw of I_STAT and a nop, then lw: AE020678
I_MASK back to 00000009
Done.

10FGR.txt

===== 10 FGR FU GPU RASTER | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 00000400
GPU: the drawing offset's wrap, GP1(10h) upper bits, the C0h pad, two CLUT rows, and
last the time 42 unwaited GP0 stores take.
GPUSTAT 5606200F at the start
Tile 60h 16x1 red, drawing area x 64..95 on row 420:
Offset 0, vertex x 76 (the setup, no wrap): 16 of 32 drawn in x 64..95, first at x 76
  ............################....
Offset 500, vertex x 600 (sum 1100): 0 of 32 drawn in x 64..95
  ................................
Offset 1000, vertex x 100 (sum 1100): 0 of 32 drawn in x 64..95
  ................................
GP1(10h), whole words:
E1 0 (4 bit page at 0,0): E2 FFFFFFh, then index 2 five times: 000FFFFF 000FFFFF 000FFFFF 000FFFFF 000FFFFF; after reading 4 pixels (1230 1231 1232 1233): 123FFFFF
  E3 FFFFFFh, then index 3 five times: 123FFFFF 123FFFFF 123FFFFF 123FFFFF 123FFFFF; after reading the pixels again: 123FFFFF
E1 4 bit page at 512,256: E2 FFFFFFh, then index 2 five times: 123FFFFF 123FFFFF 123FFFFF 123FFFFF 123FFFFF; after reading 4 pixels (1230 1231 1232 1233): 123FFFFF
  E3 FFFFFFh, then index 3 five times: 123FFFFF 123FFFFF 123FFFFF 123FFFFF 123FFFFF; after reading the pixels again: 123FFFFF
E1 15 bit page at 768,256: E2 FFFFFFh, then index 2 five times: 123FFFFF 123FFFFF 123FFFFF 123FFFFF 123FFFFF; after reading 4 pixels (1230 1231 1232 1233): 123FFFFF
  E3 FFFFFFh, then index 3 five times: 123FFFFF 123FFFFF 123FFFFF 123FFFFF 123FFFFF; after reading the pixels again: 123FFFFF
GP0(C0h) pad halfword:
Row 408 all 2222h, row 409 all 3333h: C0h 3x1 at 100,408 reads 22222222 22222222; GPUSTAT then D6062000
Row 408 2220h, 2221h, .. 2227h, row 409 all 3333h: C0h 3x1 at 100,408 reads 22212220 22232222; GPUSTAT then D6062000
CLUT rows of gpuraster CLC, 256x1 sprites of row v 1 of the page at 576,256, CLUT at
256,y holding 4000h|i; texture cache cleared first:
15 bit mode (E1 depth 2), first 16 pixels: 0100 0302 0504 0706 0908 0B0A 0D0C 0F0E 1110 1312 1514 1716 1918 1B1A 1D1C 1F1E
Depth 3 (E1 bits 7-8 = 3), first 16 pixels: 0100 0302 0504 0706 0908 0B0A 0D0C 0F0E 1110 1312 1514 1716 1918 1B1A 1D1C 1F1E
8 bit, CLUT row overwritten with 7FFFh, second sprite with CLUT x 272 (+16), pixels 240..255: 1000 1400 1000 1000 1000 1000 1000 1000 1000 1000 0C00 1000 0C00 1000 0C00 1000
  its pixels 0..15: 7FFF 7FFF 7FFF 7FFF 7FFF 7FFF 7FFF 7FFF 7FFF 7FFF 7FFF 7FFF 7FFF 7FFF 7FFF 7FFF
The zigzag polyline of 40 vertices, 42 GP0 stores with no wait:
  42 stores took 531 cycles, the GPU idle by 86867; crc C26F23A4, 54 drawn
Waits that ran out: 1
Done.

11FCD.txt

===== 11 FCD FU CD NO DISC | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 00000400
CD-ROM, no disc: parameters left by an invalid command, Init's mode, Reset's deaf
window (last). Times are cycles from the command's write.
Switches (Test 21h, bit1 door open, bit0 head at POS0): int3 03 @27636. Getstat: int3 10 @30559. Mode 20. HINTMSK was 1F.
2 parameters then command 40h: int5 11 40 @22867; HSTS after its acknowledge 11; 0 cycles later HSTS 11; Getstat: int5 11 20 @35146
2 parameters then command 40h: int5 11 40 @36847; HSTS after its acknowledge 11; 10000 cycles later HSTS 11; Getstat: int5 11 20 @32983
2 parameters then command 40h: int5 11 40 @27245; HSTS after its acknowledge 11; 100000 cycles later HSTS 11; Getstat: int5 11 20 @27767
Init (0Ah): int3 10 @51873 | int2 10 @77473; Getparam then gives mode 20
Reset (1Ch), then a Getstat:
  Reset: int3 10 @20004; Getstat sent at 50000: none
Reset (1Ch), then a Getstat:
  Reset: int3 10 @25903; Getstat sent at 100000: none
Reset (1Ch), then a Getstat:
  Reset: int3 10 @24275; Getstat sent at 200000: none
Reset (1Ch), then a Getstat:
  Reset: int3 10 @17265; Getstat sent at 300000: none
Reset (1Ch), then a Getstat:
  Reset: int3 10 @16365; Getstat sent at 600000: none
Reset (1Ch), then a Getstat:
  Reset: int3 10 @20330; Getstat sent at 1200000: none
Done.

12FMR.txt

===== 12 FMR FU MDEC DMA RESET | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 00000400
MDEC by DMA after a reset, then a CPU store to a full input FIFO. Each step saves the
log first.
One decode by DMA, the reset writes, then DMA0 alone:
  Tables by DMA0: quant 16 words timeout, scale 32 words timeout; mono 8 bit decode of 1 block to DMA1: output word 0 CCCCCCCC, status A004000D (DMA1 timed out)
  Reset 80000000h: status A0040000
  MDEC1 80000000h: status before A0000000, after 80040000
  MDEC1 60000000h: status before 80040000, after 80040000
  MDEC0 40000000h: status before 80040000, after B004000F
  DMA0 alone, 16 words of quant: 77, 1 polls; status 8004FFFF, CHCR0 00000201 BCR0 00000010 MADR0 start64
A 33rd input word with bit 30 set:
  32 words written while bit 30 was clear, status E60400DF; the next word's store between timer 2 8 and 31; status then E60400DF; 0 words read out after, last 00000000, status E60400DF
Done.

27 September 2026 run 2

00RUN.txt

===== 00 RUN | BIOS 19951204 System ROM Version 3.0 11/18/96 A
11 tests
A chain program, linked at 80100000
Saved on the card in slot 2, from image 1
COP0 at start: BPC 00000000 BDA 00000000 TAR BFC02BAC DCIC 00000000 BadVaddr 00000400 BDAM 00000000
BPCM 00000000 SR 00000000 Cause 00000020 EPC 80016C84 PRId 00000002

01FTS.txt

===== 01 FTS FU TIMER2 STOPPED | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 00000400
Timer2 stopped (mode 0001h: sync on, sync mode 0). Each row: the target written, mode
0001h written and read once, the counter written, 500 cycles, then the mode read once.
Bit 11 (0800h) is reached target, bit 12 (1000h) reached FFFFh.
Target 8000, counter written 1234: mode reads 0401, counter reads 1234
Target 8000, counter written 7FFF: mode reads 0401, counter reads 7FFF
Target 8000, counter written 8000: mode reads 0C01, counter reads 8000
Target 8000, counter written 8001: mode reads 0401, counter reads 8001
Target 8000, counter written FFFF: mode reads 0401, counter reads FFFF
Target 8000, counter written 0000: mode reads 0401, counter reads 0000
Target 1234, counter written 1234: mode reads 0C01, counter reads 1234
Target 1234, counter written 1233: mode reads 0401, counter reads 1233
Done.

02FTM.txt

===== 02 FTM FU TIMER MODE READS | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 00000400
Timer0 system clock, mode 0000 written then the counter read at once, 8 times: 0 0 0 0 0 0 0 0
Timer1 system clock, mode 0000 written then the counter read at once, 8 times: 0 0 0 0 0 0 0 0
Timer2 system clock, mode 0000 written then the counter read at once, 8 times: 0 0 0 0 0 0 0 0
Timer1 hblank clock, mode 0100 written then the counter read at once, 8 times: 0 0 0 0 0 0 0 0
Timer0 dotclock, mode 0100 written then the counter read at once, 8 times: 0 0 0 0 0 0 0 0
Done.

03FVB.txt

===== 03 FVB FU T1 VBLANK EDGE | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 00000400
Timer1 sync mode 1 (reset at vblank), set at the vblank IRQ (I_STAT bit 0); timer 2
counts system cycles from then. Where timer 1 first reads lower than before is the reset.
Timer1 system clock, sync mode 1 (mode 0003h):
  Timer1 read 49424 then 10 at 49457 cycles after the vblank IRQ (the read before at 49416)
  Timer1 read 49450 then 30 at 49495 cycles after the vblank IRQ (the read before at 49454)
  Timer1 read 49453 then 28 at 49498 cycles after the vblank IRQ (the read before at 49457)
  Timer1 read 49453 then 27 at 49498 cycles after the vblank IRQ (the read before at 49457)
Timer1 hblank clock, sync mode 1 (mode 0103h):
  Timer1 read 24 then 0 at 52034 cycles after the vblank IRQ (the read before at 51993)
  Timer1 read 24 then 0 at 52044 cycles after the vblank IRQ (the read before at 52003)
  Timer1 read 24 then 0 at 52036 cycles after the vblank IRQ (the read before at 51995)
  Timer1 read 24 then 0 at 52040 cycles after the vblank IRQ (the read before at 51999)
Timer1 hblank clock free run (mode 0100h) zeroed at one vblank IRQ, read at the next: 263 263 263 263
Done.

04FDI.txt

===== 04 FDI FU DICR LATENCY | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 00000400
IRQ3 masked in I_MASK, interrupts off. DICR written, then eight loads of I_STAT, each
followed by a load of timer 2.
DICR 00000000 written; then I_STAT bit 3 and timer 2 (cycles since just before the write): 0@15 0@36 0@78 0@99 0@135 0@156 0@192 0@213
DICR 00008000 written; then I_STAT bit 3 and timer 2 (cycles since just before the write): 0@5 1@23 1@57 1@78 1@114 1@135 1@171 1@189
DICR 00008000 written; then I_STAT bit 3 and timer 2 (cycles since just before the write): 0@5 1@23 1@57 1@78 1@114 1@141 1@177 1@195
DICR 00008000 written; then I_STAT bit 3 and timer 2 (cycles since just before the write): 0@5 1@23 1@57 1@78 1@114 1@135 1@171 1@189
DICR was 00000000 and is back to 0, then its enables.
Done.

05FGT.txt

===== 05 FGT FU GTE IR0 OPCODES | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 00000400
IR0 at the edge (the gteres RTPS inputs, V0 100h,100h,10h, DQA 0):
RTPS sf 1, DQA 0, DQB 1000000: IR0 1000, MAC0 1000000, FLAG 00000000; changed: 8=1000 9=166 10=a1 11=803 14=a000f9 19=803 24=1000000 25=166 26=a1 27=803 28=4022 F=0
RTPS sf 1, DQA 0, DQB 0FFFFFF: IR0 FFF, MAC0 FFFFFF, FLAG 00000000; changed: 8=fff 9=166 10=a1 11=803 14=a000f9 19=803 24=ffffff 25=166 26=a1 27=803 28=4022 F=0
RTPS sf 1, DQA 0, DQB 1000FFF: IR0 1000, MAC0 1000FFF, FLAG 00001000; changed: 8=1000 9=166 10=a1 11=803 14=a000f9 19=803 24=1000fff 25=166 26=a1 27=803 28=4022 F=1000
Every opcode 00h-3Fh with sf 1 and sf 0, lm 0, no other bits, each on the same seeded
inputs as gteres GNA (seed 5501AA00, SXYP IRGB ORGB LZCR not written); the registers
the command changed as <register>=<hex> (0-31 data, 32-63 control), then F=FLAG:
op 00 sf 1: 8=0 9=ffff8000 10=7fff 11=ffff8000 12=1000 14=3fffc00 16=29cd 17=e9f7 18=c3a3 19=0 24=22632822 25=89bcdadc 26=3b542ced 27=80014e52 28=3e0 F=81c7f000
op 00 sf 0: 8=0 9=ffff8000 10=7fff 12=1000 14=3fffc00 16=29cd 17=e9f7 18=c3a3 19=0 24=22632822 25=cdadc000 26=42ced12c 27=14e522f2 F=81c7f000
op 01 sf 1: 8=0 9=ffff8000 10=7fff 11=ffff8000 12=1000 14=3fffc00 16=29cd 17=e9f7 18=c3a3 19=0 24=22632822 25=89bcdadc 26=3b542ced 27=80014e52 28=3e0 F=81c7f000
op 01 sf 0: 8=0 9=ffff8000 10=7fff 12=1000 14=3fffc00 16=29cd 17=e9f7 18=c3a3 19=0 24=22632822 25=cdadc000 26=42ced12c 27=14e522f2 F=81c7f000
op 02 sf 1: 8=0 9=ffff8000 10=7fff 12=1000 14=3fffc00 16=29cd 17=e9f7 18=c3a3 19=0 24=22632822 25=89bcdadc 26=3b542ced F=81c7f000
op 02 sf 0: 8=0 9=ffff8000 10=7fff 12=1000 14=3fffc00 16=29cd 17=e9f7 18=c3a3 19=0 24=22632822 25=cdadc000 26=42ced12c F=81c7f000
op 03 sf 1: 8=0 10=7fff 12=1000 14=3ff03ff 16=29cd 17=e9f7 18=c3a3 19=0 24=22632822 26=3b542ced F=8083f000
op 03 sf 0: 8=0 10=7fff 12=1000 14=3ff03ff 16=29cd 17=e9f7 18=c3a3 19=0 24=22632822 26=42ced12c F=8083f000
op 04 sf 1: 8=0 12=1000 14=3fffffe 24=22632822 F=8000b000
op 04 sf 0: 8=0 12=1000 14=3fffffe 24=22632822 F=8000b000
op 05 sf 1: 8=0 9=ffff8000 10=7fff 12=1000 14=3fffc00 16=29cd 17=e9f7 18=c3a3 19=0 24=22632822 25=cdadc000 26=42ced12c 27=14e522f2 F=81c7f000
op 05 sf 0: 8=0 9=ffff8000 10=7fff 12=1000 14=3fffc00 16=29cd 17=e9f7 18=c3a3 19=0 24=22632822 25=cdadc000 26=42ced12c 27=14e522f2 F=81c7f000
op 06 sf 1: 24=0 F=0
op 06 sf 0: 24=0 F=0
op 07 sf 1: 24=b5cef000 F=80008000
op 07 sf 0: 24=e0f76fff F=0
op 08 sf 1: 24=8a64efff F=0
op 08 sf 0: 24=f8659721 F=0
op 09 sf 1: 24=ac5defff F=0
op 09 sf 0: 24=ac5defff F=0
op 0A sf 1: 24=7d9bb94e F=80008000
op 0A sf 0: 24=eb9c6070 F=0
op 0B sf 1: 9=7fff 10=7fff 20=7fffffff 21=7fffffff 22=7fffffff 24=dceeffff 25=8000 26=54f39001 27=1a48fc8d 28=7fff F=81f80000
op 0B sf 0: 9=7fff 10=7fff 20=7fffffff 21=7fffffff 22=7fffffff 24=a8557fff 25=8000 26=54f39001 27=1a48fc8d 28=7fff F=81f80000
op 0C sf 1: 9=2fcf 10=7fff 11=ffff8001 25=2fcf 26=3fff0 27=ffff8001 28=3ff F=80800000
op 0C sf 0: 9=7fff 10=7fff 11=ffff8000 25=2fcfa06 26=3fff0001 27=f80015fa 28=3ff F=81c00000
op 0D sf 1: 9=ffff8000 10=7fff 11=ffff8001 25=fffa0558 26=3fff0 27=ffff8001 28=3e0 F=81800000
op 0D sf 0: 9=ffff8000 10=7fff 11=ffff8000 25=8ecd0fff 26=3fff0001 27=f80015fa 28=3e0 F=81c00000
op 0E sf 1: 10=7fff 11=ffff8000 26=3ffe8 27=fffdabf1 28=3e0 F=80c00000
op 0E sf 0: 10=ffff8000 26=bffe0001 27=6afc15f9 28=7c00 F=80c00000
op 0F sf 1: 9=ffff8000 10=7fff 20=7fffffff 21=7fffffff 22=7fffff00 25=c8010000 26=54f32002 27=2b3025ea F=89f80000
op 0F sf 0: 9=7fff 10=7fff 20=7fffffff 21=7fffffff 22=7fffffff 25=48008000 26=54f42001 27=48d4c8d 28=7fff F=81f80000
op 10 sf 1: 10=7fff 11=0 20=b3b04688 21=1000 22=7f00ff00 25=ffffffff 26=87ef 27=0 28=3e0 F=80b00000
op 10 sf 0: 9=ffff8000 10=7fff 11=ffff8000 20=b3b04688 21=1000 22=7f00ff00 25=f8ff0000 26=87ef000 27=f8ff0000 28=3e0 F=81f80000
op 11 sf 1: 10=7fff 11=0 20=b3b04688 21=1000 22=7f00ff00 25=ffffffff 26=8fff 27=0 28=3e0 F=80b00000
op 11 sf 0: 9=fffff000 10=7fff 11=fffff000 20=b3b04688 21=1000 22=7f00ff00 25=fffff000 26=8fff000 27=fffff000 28=3e0 F=80f80000
op 12 sf 1: 9=ffff8000 10=7fff 11=ffff8000 25=89bcdadc 26=3b542ced 27=80014e52 28=3e0 F=81c00000
op 12 sf 0: 9=ffff8000 10=7fff 25=cdadc000 26=42ced12c 27=14e522f2 F=81c00000
op 13 sf 1: 9=fffffffe 10=407f 11=0 20=b3b04688 21=1000 22=7f00ff00 25=fffffffe 26=407f 27=0 28=3e0 F=89f00000
op 13 sf 0: 9=ffff8000 10=7fff 11=ffff8000 20=b3b04688 21=1000 22=7f00ff00 25=fff7f010 26=bf7e810 27=fff7f010 28=3e0 F=c9f80000
op 14 sf 1: 10=407f 11=0 20=b3b04688 21=1000 22=7f00ff00 25=ffffffff 26=407f 27=0 28=3e0 F=81f00000
op 14 sf 0: 9=ffff8000 10=7fff 11=ffff8000 20=b3b04688 21=1000 22=7f00ff00 25=fff7f010 26=bf7e810 27=fff7f010 28=3e0 F=81f80000
op 15 sf 1: 9=fffffffe 10=7fff 11=ffffffff 20=b3b04688 21=1000 22=7f00ff00 25=fffffffe 26=bf7e 27=ffffffff 28=3e0 F=80b80000
op 15 sf 0: 9=ffff8000 10=7fff 11=ffff8000 20=b3b04688 21=1000 22=7f00ff00 25=fff7f010 26=bf7e810 27=fff7f010 28=3e0 F=81f80000
op 16 sf 1: 9=fffffffe 10=407f 11=0 20=7f00ff00 21=7f00ff00 22=7f00ff00 25=fffffffe 26=407f 27=0 28=3e0 F=89f00000
op 16 sf 0: 9=ffff8000 10=7fff 11=ffff8000 20=7f00ff00 21=7f00ff00 22=7f00ff00 25=fff7f010 26=bf7e810 27=fff7f010 28=3e0 F=c9f80000
op 17 sf 1: 10=407f 11=0 20=7f00ff00 21=7f00ff00 22=7f00ff00 25=ffffffff 26=407f 27=0 28=3e0 F=89f00000
op 17 sf 0: 9=ffff8000 10=7fff 11=ffff8000 20=7fffff00 21=7fffff00 22=7f00ff00 25=fff7f010 26=bf7e810 27=fff7f010 28=3e0 F=c9f80000
op 18 sf 1: 9=fffffffe 10=7fff 11=ffffffff 20=7f00ff00 21=7f00ff00 22=7f00ff00 25=fffffffe 26=87ef 27=ffffffff 28=3e0 F=80b80000
op 18 sf 0: 9=ffff8000 10=7fff 11=ffff8000 20=7fffff00 21=7fffff00 22=7f00ff00 25=fffef010 26=87ef000 27=fff7f010 28=3e0 F=81f80000
op 19 sf 1: 9=fffffffe 10=7fff 11=ffffffff 20=1000 21=7f00ff00 22=7f00ff00 25=fffffffe 26=87ef 27=ffffffff 28=3e0 F=80b80000
op 19 sf 0: 9=ffff8000 10=7fff 11=ffff8000 20=1000 21=7fffff00 22=7f00ff00 25=fffef010 26=87ef000 27=fff7f010 28=3e0 F=81f80000
op 1A sf 1: 9=fffffffe 10=7fff 11=ffffffff 20=b3b04688 21=1000 22=7f00ff00 25=fffffffe 26=87ef 27=ffffffff 28=3e0 F=80b80000
op 1A sf 0: 9=ffff8000 10=7fff 11=ffff8000 20=b3b04688 21=1000 22=7f00ff00 25=fffef010 26=87ef000 27=fff7f010 28=3e0 F=81f80000
op 1B sf 1: 9=7f7f 10=ffffc080 11=ffff8080 20=b3b04688 21=1000 22=7f0000ff 25=7f7f 26=ffffc080 27=ffff8080 28=1f F=89f80000
op 1B sf 0: 9=7fff 10=7fff 20=b3b04688 21=1000 22=7fffffff 25=7f7f010 26=3f7f810 27=7f7f010 28=7fff F=c9f80000
op 1C sf 1: 9=ffff8080 10=ffffc080 11=ffff8080 20=b3b04688 21=1000 22=7f000000 25=ffff8080 26=ffffc080 27=ffff8080 28=0 F=81f80000
op 1C sf 0: 9=7fff 10=7fff 20=b3b04688 21=1000 22=7fffffff 25=7f7f010 26=3f7f810 27=7f7f010 28=7fff F=81f80000
op 1D sf 1: 9=7f7f 10=3f7f 11=7f7f 20=b3b04688 21=1000 22=7fffffff 25=7f7f 26=3f7f 27=7f7f 28=7fff F=380000
op 1D sf 0: 9=7fff 10=7fff 20=b3b04688 21=1000 22=7fffffff 25=7f7f010 26=3f7f810 27=7f7f010 28=7fff F=81f80000
op 1E sf 1: 9=7fff 10=ffff8000 11=ffff8000 20=b3b04688 21=1000 22=7f0000ff 25=7fffbc38 26=c6c54f47 27=91147f57 28=1f F=89f80000
op 1E sf 0: 9=7fff 10=7fff 20=b3b04688 21=1000 22=7fffffff 25=8008000 26=54f42001 27=11c8cc8d 28=7fff F=c9f80000
op 1F sf 1: 9=ffff8000 10=ffff8000 11=ffff8000 20=b3b04688 21=1000 22=7f000000 25=80008008 26=c6c54f42 27=91111c8c 28=0 F=c9f80000
op 1F sf 0: 9=7fff 10=7fff 20=b3b04688 21=1000 22=7fffffff 25=8008000 26=54f42001 27=11c8cc8d 28=7fff F=c9f80000
op 20 sf 1: 9=7fff 10=ffff8000 11=ffff8000 20=7f0000ff 21=7f0000ff 22=7f0000ff 25=7ffd9240 26=c6c54f44 27=9115b687 28=1f F=89f80000
op 20 sf 0: 9=7fff 10=7fff 20=7fffffff 21=7fffffff 22=7fffffff 25=8008000 26=54f42001 27=11c8cc8d 28=7fff F=c9f80000
op 21 sf 1: 9=ffff8000 10=ffff8000 11=ffff8000 20=7f000000 21=7f000000 22=7f000000 25=80000008 26=c6c54f39 27=9111a48f 28=0 F=c9f80000
op 21 sf 0: 9=7fff 10=7fff 20=7fffffff 21=7fffffff 22=7fffffff 25=8000 26=54f39001 27=1a48fc8d 28=7fff F=c9f80000
op 22 sf 1: 9=ffff8000 10=ffff8000 11=ffff8000 20=7f0000ff 21=7f000000 22=7f000000 25=80000008 26=c6c54f39 27=9111a48f 28=0 F=c9f80000
op 22 sf 0: 9=7fff 10=7fff 20=7fffff00 21=7fffffff 22=7fffffff 25=8000 26=54f39001 27=1a48fc8d 28=7fff F=c9f80000
op 23 sf 1: 9=ffff8000 10=ffff8000 11=ffff8000 20=7f002311 21=7f000000 22=7f000000 25=80000008 26=c6c54f39 27=9111a48f 28=0 F=c9f80000
op 23 sf 0: 9=7fff 10=7fff 20=7fff2311 21=7fffffff 22=7fffffff 25=8000 26=54f39001 27=1a48fc8d 28=7fff F=c9f80000
op 24 sf 1: 9=ffff8000 10=ffff8000 11=ffff8000 20=1000 21=7f000000 22=7f000000 25=80000008 26=c6c54f39 27=9111a48f 28=0 F=c9f80000
op 24 sf 0: 9=7fff 10=7fff 20=1000 21=7fffffff 22=7fffffff 25=8000 26=54f39001 27=1a48fc8d 28=7fff F=c9f80000
op 25 sf 1: 9=ffff8000 10=ffff8000 11=ffff8000 20=b3b04688 21=1000 22=7f000000 25=80000008 26=c6c54f39 27=9111a48f 28=0 F=81f80000
op 25 sf 0: 9=7fff 10=7fff 20=b3b04688 21=1000 22=7fffffff 25=8000 26=54f39001 27=1a48fc8d 28=7fff F=81f80000
op 26 sf 1: 10=ffff8000 11=ffff8000 20=b3b04688 21=1000 22=7f0000ff 26=c6c54f39 27=9111a48f 28=0 F=80d80000
op 26 sf 0: 10=7fff 20=b3b04688 21=1000 22=7fffffff 26=54f39001 27=1a48fc8d F=80d80000
op 27 sf 1: 11=ffff8000 20=b3b04688 21=1000 22=7f002311 27=9111a48f 28=3e0 F=480000
op 27 sf 0: 20=b3b04688 21=1000 22=7fff2311 27=1a48fc8d F=480000
op 28 sf 1: 9=0 25=0 26=1000 27=3fff0 F=400000
op 28 sf 0: 9=1 10=7fff 25=1 26=1000000 27=3fff0001 F=80c00000
op 29 sf 1: 9=fffffffe 10=7fff 11=ffffffff 20=b3b04688 21=1000 22=7f00ff00 25=fffffffe 26=87ef 27=ffffffff 28=3e0 F=80b80000
op 29 sf 0: 9=ffff8000 10=7fff 11=ffff8000 20=b3b04688 21=1000 22=7f00ff00 25=fffef010 26=87ef000 27=fff7f010 28=3e0 F=81f80000
op 2A sf 1: 10=7fff 11=0 20=7f00ff00 21=7f00ff00 22=7f00ff00 25=ffffffff 26=80ff 27=0 28=3e0 F=80b00000
op 2A sf 0: 9=ffff8000 10=7fff 11=0 20=7f00ff00 21=7f00ff00 22=7f00ff00 25=ff000000 26=80ff000 27=0 28=3e0 F=81f80000
op 2B sf 1: 10=7fff 11=0 20=7f00ff00 22=7f00ff00 25=ffffffff 26=80ff 27=0 28=3e0 F=80b00000
op 2B sf 0: 9=ffff8000 10=7fff 11=0 20=7f00ff00 22=7f00ff00 25=ff000000 26=80ff000 27=0 28=3e0 F=81f80000
op 2C sf 1: 20=7f00ff00 F=80b00000
op 2C sf 0: 20=7f00ff00 F=81f80000
op 2D sf 1: 7=0 24=ef21e181 F=80040000
op 2D sf 0: 7=0 24=ef21e181 F=80040000
op 2E sf 1: 7=0 24=c57ae939 F=80040000
op 2E sf 0: 7=0 24=c57ae939 F=80040000
op 2F sf 1: 7=0 9=7fff 10=7fff 20=7fffffff 21=7fffffff 22=7fffffff 24=b6d8c84 25=8000 26=54f39001 27=1a48fc8d 28=7fff F=c9fc8000
op 2F sf 0: 7=0 9=7fff 10=7fff 20=7fffffff 21=7fffffff 22=7fffffff 24=df058c84 25=8000 26=54f39001 27=1a48fc8d 28=7fff F=c9fc8000
op 30 sf 1: 8=0 9=ffff8000 10=7fff 11=ffff8000 12=3fffc00 13=3fffc00 14=3fffc00 16=c3a3 17=0 18=0 19=0 24=22632822 25=89c65e89 26=3b532619 27=8000c44b 28=3e0 F=81c7f000
op 30 sf 0: 8=0 9=7fff 10=7fff 12=3fffc00 13=3ff03ff 14=3ff03ff 16=c3a3 17=0 18=0 19=0 24=22632822 25=65e89000 26=32619148 27=c44b20b 28=7fff F=81c7f000
op 31 sf 1: 8=0 9=ffff8000 10=7fff 11=ffff8000 12=3fffc00 13=3fffc00 14=3fffc00 16=c3a3 17=0 18=0 19=0 24=22632822 25=89c65e89 26=3b532619 27=8000c44b 28=3e0 F=81c7f000
op 31 sf 0: 8=0 9=7fff 10=7fff 12=3fffc00 13=3ff03ff 14=3ff03ff 16=c3a3 17=0 18=0 19=0 24=22632822 25=65e89000 26=32619148 27=c44b20b 28=7fff F=81c7f000
op 32 sf 1: 8=0 9=ffff8000 10=7fff 11=ffff8000 12=3fffc00 13=3fffc00 14=3fffc00 16=c3a3 17=0 18=0 19=0 24=22632822 25=89c65e89 26=3b532619 27=8000c44b 28=3e0 F=81c7f000
op 32 sf 0: 8=0 9=7fff 10=7fff 12=3fffc00 13=3ff03ff 14=3ff03ff 16=c3a3 17=0 18=0 19=0 24=22632822 25=65e89000 26=32619148 27=c44b20b 28=7fff F=81c7f000
op 33 sf 1: 8=0 9=ffff8000 10=7fff 11=ffff8000 12=3fffc00 13=3fffc00 14=3fffc00 16=c3a3 17=0 18=0 19=0 24=22632822 25=89c65e89 26=3b532619 27=8000c44b 28=3e0 F=81c7f000
op 33 sf 0: 8=0 9=7fff 10=7fff 12=3fffc00 13=3ff03ff 14=3ff03ff 16=c3a3 17=0 18=0 19=0 24=22632822 25=65e89000 26=32619148 27=c44b20b 28=7fff F=81c7f000
op 34 sf 1: 8=0 9=ffff8000 10=7fff 11=ffff8000 12=3fffc00 13=3fffc00 14=3fffc00 16=e9f7 17=c3a3 18=0 19=0 24=22632822 25=89c65e89 26=3b532619 27=8000c44b 28=3e0 F=81c7f000
op 34 sf 0: 8=0 9=7fff 10=7fff 12=3fffc00 13=3ff03ff 14=3ff03ff 16=e9f7 17=c3a3 18=0 19=0 24=22632822 25=65e89000 26=32619148 27=c44b20b 28=7fff F=81c7f000
op 35 sf 1: 8=0 9=ffff8000 10=7fff 12=3fffc00 13=3fffc00 14=3ffff99 16=e9f7 17=c3a3 18=0 19=ffff 24=9b0151c0 25=89c65e89 26=3b532619 F=81c7f000
op 35 sf 0: 8=0 9=7fff 10=7fff 12=3ffff99 13=3ff03ff 14=3ff03ff 16=e9f7 17=c3a3 18=0 19=ffff 24=9b0151c0 25=65e89000 26=32619148 28=7fff F=81c77000
op 36 sf 1: 8=0 9=ffff8000 10=7fff 12=3ffff99 13=3ff03ff 14=3fffc00 16=29cd 17=e9f7 18=c3a3 19=0 24=22632822 25=89c65e89 26=3b532619 F=8183f000
op 36 sf 0: 8=0 9=7fff 10=7fff 12=3fffc00 13=3ff03ff 14=3ff03ff 16=29cd 17=e9f7 18=c3a3 19=0 24=22632822 25=65e89000 26=32619148 28=7fff F=8183f000
op 37 sf 1: 8=0 10=7fff 12=3fffc00 13=3ff03ff 14=3ff03ff 16=29cd 17=e9f7 18=c3a3 19=0 24=22632822 26=3b532619 F=8083f000
op 37 sf 0: 8=0 10=7fff 12=3fffc00 13=3ff03ff 14=3ff03ff 16=29cd 17=e9f7 18=c3a3 19=0 24=22632822 26=32619148 F=8083f000
op 38 sf 1: 8=0 10=7fff 12=3fffc00 13=3ff03ff 14=3ff03ff 16=29cd 17=e9f7 18=c3a3 19=0 24=22632822 26=3b532619 F=8083f000
op 38 sf 0: 8=0 10=7fff 12=3fffc00 13=3ff03ff 14=3ff03ff 16=29cd 17=e9f7 18=c3a3 19=0 24=22632822 26=32619148 F=8083f000
op 39 sf 1: 8=0 12=3fffc00 13=3ff03ff 14=3fffffe 16=29cd 17=e9f7 18=c3a3 19=0 24=22632822 F=8001f000
op 39 sf 0: 8=0 12=3fffc00 13=3ff03ff 14=3fffffe 16=29cd 17=e9f7 18=c3a3 19=0 24=22632822 F=8001f000
op 3A sf 1: 8=0 12=1000 13=3ff03ff 14=3fffffe 16=29cd 17=e9f7 18=c3a3 19=0 24=22632822 F=8001f000
op 3A sf 0: 8=0 12=1000 13=3ff03ff 14=3fffffe 16=29cd 17=e9f7 18=c3a3 19=0 24=22632822 F=8001f000
op 3B sf 1: 8=0 12=1000 14=3fffffe 24=22632822 F=8000b000
op 3B sf 0: 8=0 12=1000 14=3fffffe 24=22632822 F=8000b000
op 3C sf 1: 8=0 9=ffff8000 10=7fff 12=1000 14=3fffc00 16=29cd 17=e9f7 18=c3a3 19=0 24=22632822 25=cdadc000 26=42ced12c 27=14e522f2 F=81c7f000
op 3C sf 0: 8=0 9=ffff8000 10=7fff 12=1000 14=3fffc00 16=29cd 17=e9f7 18=c3a3 19=0 24=22632822 25=cdadc000 26=42ced12c 27=14e522f2 F=81c7f000
op 3D sf 1: 20=b3b04688 21=1000 22=7fffff00 25=ffffffff 26=1000 27=7fff F=380000
op 3D sf 0: 9=fffff000 10=7fff 20=b3b04688 21=1000 22=7fffff00 25=fffff000 26=1000000 27=7fff000 F=80f80000
op 3E sf 1: 9=7fff 10=ffff8000 20=b3b04688 21=1000 22=7fff00ff 25=53157f31 26=db67a9fc 27=43e637f3 28=7c1f F=81f80000
op 3E sf 0: 9=7fff 10=ffff8000 20=b3b04688 21=1000 22=7fff00ff 25=53156f32 26=dc6799fc 27=4be5a7f4 28=7c1f F=81f80000
op 3F sf 1: 9=7f7f 10=ffffc080 11=ffff8080 20=7f0000ff 21=7f0000ff 22=7f0000ff 25=7f7f 26=ffffc080 27=ffff8080 28=1f F=89f80000
op 3F sf 0: 9=7fff 10=7fff 20=7fffffff 21=7fffffff 22=7fffffff 25=7f7f010 26=3f7f810 27=7f7f010 28=7fff F=c9f80000
Done.

06FMD.txt

===== 06 FMD FU MDEC RESET COLOUR | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 00000400
Reset timing: MDEC1 written 80000000h, then MDEC1 read eight times, each followed by
a timer 2 read (cycles since just before the write).
Idle, status after the reset write @ timer 2: 80040000@15 80040000@35 80040000@53 80040000@71 80040000@89 80040000@107 80040000@129 80040000@147
15 bit decode with the input full, nothing read, status after the reset write @ timer 2: E60400DF@15 80040000@35 80040000@53 80040000@71 80040000@99 80040000@117 80040000@135 80040000@153
Short decode counts by CPU (mdecout ODD's way): the 4bit/8bit block at 8 bit with its
tables, the step stream at 15 bit with its tables. Only `count` words are written.
8 bit, decode count 1, 1 words written: 48 words out, CRC A9DEB035, status 8204FFFF, first 8F9EA9AF last 118AFF72
8 bit, decode count 2, 2 words written: 32 words out, CRC F60B4B13, status 8204FFFF, first FFFB7B20 last 118AFF72
15 bit, decode count 4, 4 words written: 32 words out, CRC C2A8FA9D, status 8601FFFF, first 00000000 last 00000000
15 bit, decode count 5, 5 words written: 32 words out, CRC C2A8FA9D, status 8601FFFF, first 00000000 last 00000000
15 bit, decode count 6, 6 words written: 32 words out, CRC C2A8FA9D, status 8601FFFF, first 00000000 last 00000000
Colour matrix and clamp: one macroblock of DC-only blocks, Cr and Cb and all four Y as
given (10 bit DC values), quant table all 4, the standard scale table, unsigned, by CPU.
The first output word of each 8x8 quadrant at 24 bit and at 15 bit.
Cr -256 Cb -256 Y 0: 24 bit 192 words, 0000FF00 0000FF00 0000FF00 0000FF00; 15 bit 128 words, 03E003E0 03E003E0 03E003E0 03E003E0
Cr -256 Cb -64 Y 0: 24 bit 192 words, 0047E700 0047E700 0047E700 0047E700; 15 bit 128 words, 27A027A0 27A027A0 27A027A0 27A027A0
Cr -256 Cb 0 Y 0: 24 bit 192 words, 0080DC00 0080DC00 0080DC00 0080DC00; 15 bit 128 words, 43604360 43604360 43604360 43604360
Cr -256 Cb 64 Y 0: 24 bit 192 words, 00B9D100 00B9D100 00B9D100 00B9D100; 15 bit 128 words, 5F405F40 5F405F40 5F405F40 5F405F40
Cr -256 Cb 255 Y 0: 24 bit 192 words, 00FFB000 00FFB000 00FFB000 00FFB000; 15 bit 128 words, 7EC07EC0 7EC07EC0 7EC07EC0 7EC07EC0
Cr -64 Cb -256 Y 0: 24 bit 192 words, 5300C353 5300C353 5300C353 5300C353; 15 bit 128 words, 030A030A 030A030A 030A030A 030A030A
Cr -64 Cb -64 Y 0: 24 bit 192 words, 5347A253 5347A253 5347A253 5347A253; 15 bit 128 words, 268A268A 268A268A 268A268A 268A268A
Cr -64 Cb 0 Y 0: 24 bit 192 words, 53809753 53809753 53809753 53809753; 15 bit 128 words, 426A426A 426A426A 426A426A 426A426A
Cr -64 Cb 64 Y 0: 24 bit 192 words, 53B98C53 53B98C53 53B98C53 53B98C53; 15 bit 128 words, 5E2A5E2A 5E2A5E2A 5E2A5E2A 5E2A5E2A
Cr -64 Cb 255 Y 0: 24 bit 192 words, 53FF6B53 53FF6B53 53FF6B53 53FF6B53; 15 bit 128 words, 7DAA7DAA 7DAA7DAA 7DAA7DAA 7DAA7DAA
Cr 0 Cb -256 Y 0: 24 bit 192 words, 8000AC80 8000AC80 8000AC80 8000AC80; 15 bit 128 words, 02D002D0 02D002D0 02D002D0 02D002D0
Cr 0 Cb -64 Y 0: 24 bit 192 words, 80478B80 80478B80 80478B80 80478B80; 15 bit 128 words, 26302630 26302630 26302630 26302630
Cr 0 Cb 0 Y 0: 24 bit 192 words, 80808080 80808080 80808080 80808080; 15 bit 128 words, 42104210 42104210 42104210 42104210
Cr 0 Cb 64 Y 0: 24 bit 192 words, 80B97580 80B97580 80B97580 80B97580; 15 bit 128 words, 5DF05DF0 5DF05DF0 5DF05DF0 5DF05DF0
Cr 0 Cb 255 Y 0: 24 bit 192 words, 80FF5480 80FF5480 80FF5480 80FF5480; 15 bit 128 words, 7D707D70 7D707D70 7D707D70 7D707D70
Cr 64 Cb -256 Y 0: 24 bit 192 words, AD0095AD AD0095AD AD0095AD AD0095AD; 15 bit 128 words, 02760276 02760276 02760276 02760276
Cr 64 Cb -64 Y 0: 24 bit 192 words, AD4774AD AD4774AD AD4774AD AD4774AD; 15 bit 128 words, 25F625F6 25F625F6 25F625F6 25F625F6
Cr 64 Cb 0 Y 0: 24 bit 192 words, AD8069AD AD8069AD AD8069AD AD8069AD; 15 bit 128 words, 41B641B6 41B641B6 41B641B6 41B641B6
Cr 64 Cb 64 Y 0: 24 bit 192 words, ADB95EAD ADB95EAD ADB95EAD ADB95EAD; 15 bit 128 words, 5D965D96 5D965D96 5D965D96 5D965D96
Cr 64 Cb 255 Y 0: 24 bit 192 words, ADFF3DAD ADFF3DAD ADFF3DAD ADFF3DAD; 15 bit 128 words, 7D167D16 7D167D16 7D167D16 7D167D16
Cr 255 Cb -256 Y 0: 24 bit 192 words, FF0051FF FF0051FF FF0051FF FF0051FF; 15 bit 128 words, 015F015F 015F015F 015F015F 015F015F
Cr 255 Cb -64 Y 0: 24 bit 192 words, FF4730FF FF4730FF FF4730FF FF4730FF; 15 bit 128 words, 24DF24DF 24DF24DF 24DF24DF 24DF24DF
Cr 255 Cb 0 Y 0: 24 bit 192 words, FF8025FF FF8025FF FF8025FF FF8025FF; 15 bit 128 words, 40BF40BF 40BF40BF 40BF40BF 40BF40BF
Cr 255 Cb 64 Y 0: 24 bit 192 words, FFB91AFF FFB91AFF FFB91AFF FFB91AFF; 15 bit 128 words, 5C7F5C7F 5C7F5C7F 5C7F5C7F 5C7F5C7F
Cr 255 Cb 255 Y 0: 24 bit 192 words, FFFF00FF FFFF00FF FFFF00FF FFFF00FF; 15 bit 128 words, 7C1F7C1F 7C1F7C1F 7C1F7C1F 7C1F7C1F
Cr -256 Cb -256 Y -128: 24 bit 192 words, 00FFC800 00FFC800 00FFC800 00FFC800; 15 bit 128 words, 7F207F20 7F207F20 7F207F20 7F207F20
Cr -256 Cb -256 Y 127: 24 bit 192 words, 0C00FF0C 0C00FF0C 0C00FF0C 0C00FF0C; 15 bit 128 words, 03E103E1 03E103E1 03E103E1 03E103E1
Cr -256 Cb 255 Y -128: 24 bit 192 words, 00FF7000 00FF7000 00FF7000 00FF7000; 15 bit 128 words, 7DC07DC0 7DC07DC0 7DC07DC0 7DC07DC0
Cr -256 Cb 255 Y 127: 24 bit 192 words, 0C00EF0C 0C00EF0C 0C00EF0C 0C00EF0C; 15 bit 128 words, 03C103C1 03C103C1 03C103C1 03C103C1
Cr 255 Cb -256 Y -128: 24 bit 192 words, F2FF11F2 F2FF11F2 F2FF11F2 F2FF11F2; 15 bit 128 words, 7C5E7C5E 7C5E7C5E 7C5E7C5E 7C5E7C5E
Cr 255 Cb -256 Y 127: 24 bit 192 words, FF0090FF FF0090FF FF0090FF FF0090FF; 15 bit 128 words, 025F025F 025F025F 025F025F 025F025F
Cr 255 Cb 255 Y -128: 24 bit 192 words, F2FF00F2 F2FF00F2 F2FF00F2 F2FF00F2; 15 bit 128 words, 7C1E7C1E 7C1E7C1E 7C1E7C1E 7C1E7C1E
Cr 255 Cb 255 Y 127: 24 bit 192 words, FF0038FF FF0038FF FF0038FF FF0038FF; 15 bit 128 words, 00FF00FF 00FF00FF 00FF00FF 00FF00FF
Cr 0 Cb 0 Y -128: 24 bit 192 words, 40404040 40404040 40404040 40404040; 15 bit 128 words, 21082108 21082108 21082108 21082108
Cr 0 Cb 0 Y 127: 24 bit 192 words, BFBFBFBF BFBFBFBF BFBFBFBF BFBFBFBF; 15 bit 128 words, 63186318 63186318 63186318 63186318
Cr 64 Cb -64 Y -128: 24 bit 192 words, 6D07346D 6D07346D 6D07346D 6D07346D; 15 bit 128 words, 04EE04EE 04EE04EE 04EE04EE 04EE04EE
Cr 64 Cb -64 Y 127: 24 bit 192 words, EC86B3EC EC86B3EC EC86B3EC EC86B3EC; 15 bit 128 words, 46DD46DD 46DD46DD 46DD46DD 46DD46DD
Cr -64 Cb 64 Y -128: 24 bit 192 words, 13794C13 13794C13 13794C13 13794C13; 15 bit 128 words, 3D223D22 3D223D22 3D223D22 3D223D22
Cr -64 Cb 64 Y 127: 24 bit 192 words, 92F8CB92 92F8CB92 92F8CB92 92F8CB92; 15 bit 128 words, 7F327F32 7F327F32 7F327F32 7F327F32
Done.

07FSP.txt

===== 07 FSP FU SPU ENV FIFO | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 00000400
Envelope counter, one for all voices or one each: voices 0 and 1 attack linear shift
16 step 0, keyed on 1500 cycles apart; cycles from voice 0's KON.
Voice 0 keyed on at 0, voice 1 at 1636; first level changes, voice 0: 11022 35590 60142 84702; voice 1: 11022 35590 60142 84702; levels then 002A 002A
Voice 0 keyed on at 0, voice 1 at 1592; first level changes, voice 0: 17885 42429 67077 91629; voice 1: 17885 42429 67077 91629; levels then 002A 002A
Voice 0 keyed on at 0, voice 1 at 1568; first level changes, voice 0: 17866 42418 66977 91618; voice 1: 17866 42418 66977 91618; levels then 002A 002A
ADSR level times the sample: tone T on voice 1, pitch 1000h, held at 7FFFh; the level
register written, then the voice 1 capture buffer (first 16 samples).
Level as it stands, 255 changes in 256:
  FC83 FD03 FD82 FE01 FE81 FF00 FF80 FFFF 007E 00FE 017D 01FD 027C 02FC 024B FD30
Level read 3FFF
Level written 4000h, reads 4000
Level 4000h, 255 changes in 256:
  007F 00FE 017E 01FD 027D 02FC 024C FD30 FC83 FD03 FD88 FE28 FEC5 FF57 FFE1 0062
Level written 7FFFh, reads 7FFF
Level 7FFFh, 255 changes in 256:
  F907 FA06 FB11 FC50 FD8A FEAF FFC3 00C4 01B6 0299 036E 0436 04F1 05A1 0645 06DF
FIFO drain: halfwords B000h, B001h, .. to scratch at 30000h (filled EEEEh) by one DMA
block of 16 words, a wait, SPUCNT transfer mode Stop, then read back by DMA.
Wait 0 cycles after the DMA ended: 9 of 32 halfwords written, 0 still EEEEh, first B000 last 5555
Wait 100 cycles after the DMA ended: 9 of 32 halfwords written, 0 still EEEEh, first B000 last 5555
Wait 200 cycles after the DMA ended: 10 of 32 halfwords written, 0 still EEEEh, first B000 last 5555
Wait 300 cycles after the DMA ended: 15 of 32 halfwords written, 0 still EEEEh, first B000 last 5555
Wait 400 cycles after the DMA ended: 18 of 32 halfwords written, 0 still EEEEh, first B000 last 5555
Wait 500 cycles after the DMA ended: 23 of 32 halfwords written, 0 still EEEEh, first B000 last 5555
Wait 600 cycles after the DMA ended: 27 of 32 halfwords written, 0 still EEEEh, first B000 last 5555
Wait 700 cycles after the DMA ended: 32 of 32 halfwords written, 0 still EEEEh, first B000 last B01F
Wait 800 cycles after the DMA ended: 32 of 32 halfwords written, 0 still EEEEh, first B000 last B01F
Wait 900 cycles after the DMA ended: 32 of 32 halfwords written, 0 still EEEEh, first B000 last B01F
Wait 1000 cycles after the DMA ended: 32 of 32 halfwords written, 0 still EEEEh, first B000 last B01F
Wait 1100 cycles after the DMA ended: 32 of 32 halfwords written, 0 still EEEEh, first B000 last B01F
Wait 1200 cycles after the DMA ended: 32 of 32 halfwords written, 0 still EEEEh, first B000 last B01F
Wait 1300 cycles after the DMA ended: 32 of 32 halfwords written, 0 still EEEEh, first B000 last B01F
Wait 1400 cycles after the DMA ended: 32 of 32 halfwords written, 0 still EEEEh, first B000 last B01F
Wait 1500 cycles after the DMA ended: 32 of 32 halfwords written, 0 still EEEEh, first B000 last B01F
Wait 1600 cycles after the DMA ended: 32 of 32 halfwords written, 0 still EEEEh, first B000 last B01F
Start address one 8 byte unit past a block (spuenv END's S4+8 case): tone T on voice 1,
pitch 1000h, start and repeat as given; the voice 1 capture buffer.
Start 40C0h (the block), 66 changes in 256:
  0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
  0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
Start 40C1h (one unit in), 255 changes in 256:
  FE29 FDC7 FD6A FD14 FD4A FF98 007E 00FE 017D 01FD 027C 02FC 024B FD30 FC83 FD03
  FD82 FE01 FE81 FF00 FF80 FFFF 007E 00FE 017D 01FD 027C 02FC 024B FD30 FC83 FD03
Done.

08FDS.txt

===== 08 FDS FU DMA SPU BLOCKS | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 00000400
DMA4 SPU write SyncMode 1, 256 words to 30000h, cycles from the CHCR write until bit 24
clears, three times each. SPU delay register (1F801014h) was 200931E1.
Delay 200931E1, blocks of 1 words x 256: 16341 16324 16322
Delay 200931E1, blocks of 2 words x 128: 16278 16276 16319
Delay 200931E1, blocks of 4 words x 64: 18264 18300 18300
Delay 200931E1, blocks of 8 words x 32: 17032 17032 17026
Delay 200931E1, blocks of 16 words x 16: 16828 16807 16807
Delay 200931E1, blocks of 32 words x 8: 8546 8529 8529
Delay 210931E1, blocks of 1 words x 256: 16365 16330 16365
Delay 210931E1, blocks of 2 words x 128: 17240 17240 17148
Delay 210931E1, blocks of 4 words x 64: 18283 18312 18312
Delay 210931E1, blocks of 8 words x 32: 17902 17898 17930
Delay 210931E1, blocks of 16 words x 16: 17252 17542 17518
Delay 210931E1, blocks of 32 words x 8: 8578 8619 8607
Delay 220931E1, blocks of 1 words x 256: 16340 16339 16339
Delay 220931E1, blocks of 2 words x 128: 19550 19515 19515
Delay 220931E1, blocks of 4 words x 64: 18296 18313 18313
Delay 220931E1, blocks of 8 words x 32: 18664 18634 18631
Delay 220931E1, blocks of 16 words x 16: 17751 17741 17737
Delay 220931E1, blocks of 32 words x 8: 9484 9467 9467
Delay 230931E1, blocks of 1 words x 256: 16352 16450 16343
Delay 230931E1, blocks of 2 words x 128: 19565 19585 19585
Delay 230931E1, blocks of 4 words x 64: 19444 19469 19469
Delay 230931E1, blocks of 8 words x 32: 18668 18645 18645
Delay 230931E1, blocks of 16 words x 16: 17772 17770 17792
Delay 230931E1, blocks of 32 words x 8: 10193 10169 10169
SPU delay register back to 200931E1
Done.

09FSI.txt

===== 09 FSI FU SIO RXEN IMASK | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 00000400
Controller port with RXEN and no device selected (JOY_CTRL bit 1 clear), slot 1.
CTRL 0004, no data written; JOY_STAT (bits 0-10) every 100 cycles from 0 to 3000:
  005 005 005 005 005 005 005 005 005 005 005 005 005 007 007 007 007 007 007 007 007 007 007 007 007 007 007 007 007 007 007
  bytes in the RX FIFO: 1 FF; I_STAT bit 7 then 0
CTRL 0805, no data written; JOY_STAT (bits 0-10) every 100 cycles from 0 to 3000:
  005 005 005 005 005 005 005 005 005 005 005 005 005 207 207 207 207 207 207 207 207 207 207 207 207 207 207 207 207 207 207
  bytes in the RX FIFO: 1 FF; I_STAT bit 7 then 1
I_MASK's upper half (the console read 960507FFh after sw FFFFFFFFh, chainb/028/01IMR.txt:4):
sw 12345678h to I_MASK, lw at once: AD090678
sw 12345678h, lui/ori of CAFEBABEh, then lw: AD090678
sw 12345678h, lw of I_STAT and a nop, then lw: AE020678
I_MASK back to 00000009
Done.

10FGR.txt

===== 10 FGR FU GPU RASTER | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 00000400
GPU: the drawing offset's wrap, GP1(10h) upper bits, the C0h pad, two CLUT rows, and
last the time 42 unwaited GP0 stores take.
GPUSTAT 5606200F at the start
Tile 60h 16x1 red, drawing area x 64..95 on row 420:
Offset 0, vertex x 76 (the setup, no wrap): 16 of 32 drawn in x 64..95, first at x 76
  ............################....
Offset 500, vertex x 600 (sum 1100): 0 of 32 drawn in x 64..95
  ................................
Offset 1000, vertex x 100 (sum 1100): 0 of 32 drawn in x 64..95
  ................................
GP1(10h), whole words:
E1 0 (4 bit page at 0,0): E2 FFFFFFh, then index 2 five times: 000FFFFF 000FFFFF 000FFFFF 000FFFFF 000FFFFF; after reading 4 pixels (1230 1231 1232 1233): 123FFFFF
  E3 FFFFFFh, then index 3 five times: 123FFFFF 123FFFFF 123FFFFF 123FFFFF 123FFFFF; after reading the pixels again: 123FFFFF
E1 4 bit page at 512,256: E2 FFFFFFh, then index 2 five times: 123FFFFF 123FFFFF 123FFFFF 123FFFFF 123FFFFF; after reading 4 pixels (1230 1231 1232 1233): 123FFFFF
  E3 FFFFFFh, then index 3 five times: 123FFFFF 123FFFFF 123FFFFF 123FFFFF 123FFFFF; after reading the pixels again: 123FFFFF
E1 15 bit page at 768,256: E2 FFFFFFh, then index 2 five times: 123FFFFF 123FFFFF 123FFFFF 123FFFFF 123FFFFF; after reading 4 pixels (1230 1231 1232 1233): 123FFFFF
  E3 FFFFFFh, then index 3 five times: 123FFFFF 123FFFFF 123FFFFF 123FFFFF 123FFFFF; after reading the pixels again: 123FFFFF
GP0(C0h) pad halfword:
Row 408 all 2222h, row 409 all 3333h: C0h 3x1 at 100,408 reads 22222222 22222222; GPUSTAT then D6062000
Row 408 2220h, 2221h, .. 2227h, row 409 all 3333h: C0h 3x1 at 100,408 reads 22212220 22232222; GPUSTAT then 56062000
CLUT rows of gpuraster CLC, 256x1 sprites of row v 1 of the page at 576,256, CLUT at
256,y holding 4000h|i; texture cache cleared first:
15 bit mode (E1 depth 2), first 16 pixels: 0100 0302 0504 0706 0908 0B0A 0D0C 0F0E 1110 1312 1514 1716 1918 1B1A 1D1C 1F1E
Depth 3 (E1 bits 7-8 = 3), first 16 pixels: 0100 0302 0504 0706 0908 0B0A 0D0C 0F0E 1110 1312 1514 1716 1918 1B1A 1D1C 1F1E
8 bit, CLUT row overwritten with 7FFFh, second sprite with CLUT x 272 (+16), pixels 240..255: 1000 1400 1000 1000 1000 1000 1000 1000 1000 1000 0C00 1000 0C00 1000 0C00 1000
  its pixels 0..15: 7FFF 7FFF 7FFF 7FFF 7FFF 7FFF 7FFF 7FFF 7FFF 7FFF 7FFF 7FFF 7FFF 7FFF 7FFF 7FFF
The zigzag polyline of 40 vertices, 42 GP0 stores with no wait: not run in this table.
Waits that ran out: 0
Done.

11FCD.txt

===== 11 FCD FU CD NO DISC | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 00000400
CD-ROM, no disc: parameters left by an invalid command, Init's mode, Reset's deaf
window (last). Times are cycles from the command's write.
Switches (Test 21h, bit1 door open, bit0 head at POS0): int3 03 @26341. Getstat: int3 10 @28975. Mode 20. HINTMSK was 1F.
2 parameters then command 40h: int5 11 40 @21062; HSTS after its acknowledge 11; 0 cycles later HSTS 11; Getstat: int5 11 20 @28188
2 parameters then command 40h: int5 11 40 @20776; HSTS after its acknowledge 11; 10000 cycles later HSTS 11; Getstat: int5 11 20 @37066
2 parameters then command 40h: int5 11 40 @20904; HSTS after its acknowledge 11; 100000 cycles later HSTS 11; Getstat: int5 11 20 @25103
Init (0Ah): int3 10 @58586 | int2 10 @84154; Getparam then gives mode 20
Reset (1Ch), then a Getstat: not run in this table.
Reset (1Ch), then a Getstat: not run in this table.
Reset (1Ch), then a Getstat: not run in this table.
Reset (1Ch), then a Getstat: not run in this table.
Reset (1Ch), then a Getstat: not run in this table.
Reset (1Ch), then a Getstat: not run in this table.
Done.

27 September 2026 run 3

00RUN.txt

===== 00 RUN | BIOS 19951204 System ROM Version 3.0 11/18/96 A
11 tests
A chain program, linked at 80100000
Saved on the card in slot 2, from image 1
COP0 at start: BPC 00000000 BDA 80024F50 TAR 80020FC8 DCIC 00000000 BadVaddr 800154CE BDAM FFFFFFFF
BPCM 00000000 SR 40000000 Cause 00000020 EPC 80021B7C PRId 00000002

01FTS.txt

===== 01 FTS FU TIMER2 STOPPED | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 800154CE
Timer2 stopped (mode 0001h: sync on, sync mode 0). Each row: the target written, mode
0001h written and read once, the counter written, 500 cycles, then the mode read once.
Bit 11 (0800h) is reached target, bit 12 (1000h) reached FFFFh.
Target 8000, counter written 1234: mode reads 0401, counter reads 1234
Target 8000, counter written 7FFF: mode reads 0401, counter reads 7FFF
Target 8000, counter written 8000: mode reads 0C01, counter reads 8000
Target 8000, counter written 8001: mode reads 0401, counter reads 8001
Target 8000, counter written FFFF: mode reads 0401, counter reads FFFF
Target 8000, counter written 0000: mode reads 0401, counter reads 0000
Target 1234, counter written 1234: mode reads 0C01, counter reads 1234
Target 1234, counter written 1233: mode reads 0401, counter reads 1233
Done.

02FTM.txt

===== 02 FTM FU TIMER MODE READS | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 800154CE
Timer0 system clock, mode 0000 written then the counter read at once, 8 times: 0 0 0 0 0 0 0 0
Timer1 system clock, mode 0000 written then the counter read at once, 8 times: 0 0 0 0 0 0 0 0
Timer2 system clock, mode 0000 written then the counter read at once, 8 times: 0 0 0 0 0 0 0 0
Timer1 hblank clock, mode 0100 written then the counter read at once, 8 times: 0 0 0 0 0 0 0 0
Timer0 dotclock, mode 0100 written then the counter read at once, 8 times: 0 0 0 0 0 0 0 0
Done.

03FVB.txt

===== 03 FVB FU T1 VBLANK EDGE | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 800154CE
Timer1 sync mode 1 (reset at vblank), set at the vblank IRQ (I_STAT bit 0); timer 2
counts system cycles from then. Where timer 1 first reads lower than before is the reset.
Timer1 system clock, sync mode 1 (mode 0003h):
  Timer1 read 49429 then 29 at 49462 cycles after the vblank IRQ (the read before at 49421)
  Timer1 read 49453 then 28 at 49498 cycles after the vblank IRQ (the read before at 49457)
  Timer1 read 49448 then 28 at 49493 cycles after the vblank IRQ (the read before at 49452)
  Timer1 read 49453 then 27 at 49498 cycles after the vblank IRQ (the read before at 49457)
Timer1 hblank clock, sync mode 1 (mode 0103h):
  Timer1 read 24 then 0 at 52036 cycles after the vblank IRQ (the read before at 51995)
  Timer1 read 24 then 0 at 52043 cycles after the vblank IRQ (the read before at 52002)
  Timer1 read 24 then 0 at 52036 cycles after the vblank IRQ (the read before at 51995)
  Timer1 read 24 then 0 at 52040 cycles after the vblank IRQ (the read before at 51999)
Timer1 hblank clock free run (mode 0100h) zeroed at one vblank IRQ, read at the next: 263 263 263 263
Done.

04FDI.txt

===== 04 FDI FU DICR LATENCY | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 800154CE
IRQ3 masked in I_MASK, interrupts off. DICR written, then eight loads of I_STAT, each
followed by a load of timer 2.
DICR 00000000 written; then I_STAT bit 3 and timer 2 (cycles since just before the write): 0@15 0@36 0@72 0@93 0@134 0@155 0@191 0@212
DICR 00008000 written; then I_STAT bit 3 and timer 2 (cycles since just before the write): 0@5 1@23 1@57 1@78 1@114 1@135 1@175 1@193
DICR 00008000 written; then I_STAT bit 3 and timer 2 (cycles since just before the write): 0@5 1@23 1@57 1@78 1@114 1@135 1@171 1@189
DICR 00008000 written; then I_STAT bit 3 and timer 2 (cycles since just before the write): 0@5 1@23 1@57 1@78 1@114 1@135 1@171 1@189
DICR was 00000000 and is back to 0, then its enables.
Done.

05FGT.txt

===== 05 FGT FU GTE IR0 OPCODES | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 800154CE
IR0 at the edge (the gteres RTPS inputs, V0 100h,100h,10h, DQA 0):
RTPS sf 1, DQA 0, DQB 1000000: IR0 1000, MAC0 1000000, FLAG 00000000; changed: 8=1000 9=166 10=a1 11=803 14=a000f9 19=803 24=1000000 25=166 26=a1 27=803 28=4022 F=0
RTPS sf 1, DQA 0, DQB 0FFFFFF: IR0 FFF, MAC0 FFFFFF, FLAG 00000000; changed: 8=fff 9=166 10=a1 11=803 14=a000f9 19=803 24=ffffff 25=166 26=a1 27=803 28=4022 F=0
RTPS sf 1, DQA 0, DQB 1000FFF: IR0 1000, MAC0 1000FFF, FLAG 00001000; changed: 8=1000 9=166 10=a1 11=803 14=a000f9 19=803 24=1000fff 25=166 26=a1 27=803 28=4022 F=1000
Every opcode 00h-3Fh with sf 1 and sf 0, lm 0, no other bits, each on the same seeded
inputs as gteres GNA (seed 5501AA00, SXYP IRGB ORGB LZCR not written); the registers
the command changed as <register>=<hex> (0-31 data, 32-63 control), then F=FLAG:
op 00 sf 1: 8=0 9=ffff8000 10=7fff 11=ffff8000 12=1000 14=3fffc00 16=29cd 17=e9f7 18=c3a3 19=0 24=22632822 25=89bcdadc 26=3b542ced 27=80014e52 28=3e0 F=81c7f000
op 00 sf 0: 8=0 9=ffff8000 10=7fff 12=1000 14=3fffc00 16=29cd 17=e9f7 18=c3a3 19=0 24=22632822 25=cdadc000 26=42ced12c 27=14e522f2 F=81c7f000
op 01 sf 1: 8=0 9=ffff8000 10=7fff 11=ffff8000 12=1000 14=3fffc00 16=29cd 17=e9f7 18=c3a3 19=0 24=22632822 25=89bcdadc 26=3b542ced 27=80014e52 28=3e0 F=81c7f000
op 01 sf 0: 8=0 9=ffff8000 10=7fff 12=1000 14=3fffc00 16=29cd 17=e9f7 18=c3a3 19=0 24=22632822 25=cdadc000 26=42ced12c 27=14e522f2 F=81c7f000
op 02 sf 1: 8=0 9=ffff8000 10=7fff 12=1000 14=3fffc00 16=29cd 17=e9f7 18=c3a3 19=0 24=22632822 25=89bcdadc 26=3b542ced F=81c7f000
op 02 sf 0: 8=0 9=ffff8000 10=7fff 12=1000 14=3fffc00 16=29cd 17=e9f7 18=c3a3 19=0 24=22632822 25=cdadc000 26=42ced12c F=81c7f000
op 03 sf 1: 8=0 10=7fff 12=1000 14=3ff03ff 16=29cd 17=e9f7 18=c3a3 19=0 24=22632822 26=3b542ced F=8083f000
op 03 sf 0: 8=0 10=7fff 12=1000 14=3ff03ff 16=29cd 17=e9f7 18=c3a3 19=0 24=22632822 26=42ced12c F=8083f000
op 04 sf 1: 8=0 12=1000 14=3fffffe 24=22632822 F=8000b000
op 04 sf 0: 8=0 12=1000 14=3fffffe 24=22632822 F=8000b000
op 05 sf 1: 8=0 9=ffff8000 10=7fff 12=1000 14=3fffc00 16=29cd 17=e9f7 18=c3a3 19=0 24=22632822 25=cdadc000 26=42ced12c 27=14e522f2 F=81c7f000
op 05 sf 0: 8=0 9=ffff8000 10=7fff 12=1000 14=3fffc00 16=29cd 17=e9f7 18=c3a3 19=0 24=22632822 25=cdadc000 26=42ced12c 27=14e522f2 F=81c7f000
op 06 sf 1: 24=0 F=0
op 06 sf 0: 24=0 F=0
op 07 sf 1: 24=74087000 F=80008000
op 07 sf 0: 24=f4086fff F=0
op 08 sf 1: 24=c4086fff F=0
op 08 sf 0: 24=f5087000 F=0
op 09 sf 1: 24=dc086fff F=0
op 09 sf 0: 24=dc086fff F=0
op 0A sf 1: 24=c057394e F=0
op 0A sf 0: 24=f157394f F=0
op 0B sf 1: 9=7fff 10=7fff 20=7fffffff 21=7fffffff 22=7fffffff 24=efffffff 25=8000 26=54f39001 27=1a48fc8d 28=7fff F=81f80000
op 0B sf 0: 9=7fff 10=7fff 20=7fffffff 21=7fffffff 22=7fffffff 24=d7ffffff 25=8000 26=54f39001 27=1a48fc8d 28=7fff F=81f80000
op 0C sf 1: 9=2fcf 10=7fff 11=ffff8001 25=2fcf 26=3fff0 27=ffff8001 28=3ff F=80800000
op 0C sf 0: 9=7fff 10=7fff 11=ffff8000 25=2fcfa06 26=3fff0001 27=f80015fa 28=3ff F=81c00000
op 0D sf 1: 9=ffff8000 10=7fff 11=ffff8001 25=fffd0000 26=3fff0 27=ffff8001 28=3e0 F=81800000
op 0D sf 0: 9=ffff8000 10=7fff 11=ffff8000 25=c8000fff 26=3fff0001 27=f80015fa 28=3e0 F=81c00000
op 0E sf 1: 10=7fff 11=1 26=7fff0 27=1 28=3e0 F=80800000
op 0E sf 0: 10=ffff8000 11=15f9 26=8afb0001 27=15f9 28=7c00 F=80800000
op 0F sf 1: 9=7fff 10=7fff 20=7fffffff 21=7fffffff 22=7fffffff 25=48008000 26=54f42001 27=48d4c8d 28=7fff F=81f80000
op 0F sf 0: 9=7fff 10=7fff 20=7fffffff 21=7fffffff 22=7fffffff 25=48008000 26=54f42001 27=48d4c8d 28=7fff F=81f80000
op 10 sf 1: 10=7fff 11=0 20=b3b04688 21=1000 22=7f00ff00 25=ffffffff 26=87ef 27=0 28=3e0 F=80b00000
op 10 sf 0: 9=ffff8000 10=7fff 11=ffff8000 20=b3b04688 21=1000 22=7f00ff00 25=f8ff0000 26=87ef000 27=f8ff0000 28=3e0 F=81f80000
op 11 sf 1: 10=7fff 11=0 20=b3b04688 21=1000 22=7f00ff00 25=ffffffff 26=8fff 27=0 28=3e0 F=80b00000
op 11 sf 0: 9=fffff000 10=7fff 11=fffff000 20=b3b04688 21=1000 22=7f00ff00 25=fffff000 26=8fff000 27=fffff000 28=3e0 F=80f80000
op 12 sf 1: 9=ffff8000 10=7fff 11=ffff8000 25=89bcdadc 26=3b542ced 27=80014e52 28=3e0 F=81c00000
op 12 sf 0: 9=ffff8000 10=7fff 25=cdadc000 26=42ced12c 27=14e522f2 F=81c00000
op 13 sf 1: 9=fffffffe 10=407f 11=0 20=b3b04688 21=1000 22=7f00ff00 25=fffffffe 26=407f 27=0 28=3e0 F=89f00000
op 13 sf 0: 9=ffff8000 10=7fff 11=ffff8000 20=b3b04688 21=1000 22=7f00ff00 25=fff7f010 26=bf7e810 27=fff7f010 28=3e0 F=c9f80000
op 14 sf 1: 10=407f 11=0 20=b3b04688 21=1000 22=7f00ff00 25=ffffffff 26=407f 27=0 28=3e0 F=81f00000
op 14 sf 0: 9=ffff8000 10=7fff 11=ffff8000 20=b3b04688 21=1000 22=7f00ff00 25=fff7f010 26=bf7e810 27=fff7f010 28=3e0 F=81f80000
op 15 sf 1: 9=fffffffe 10=7fff 11=ffffffff 20=b3b04688 21=1000 22=7f00ff00 25=fffffffe 26=bf7e 27=ffffffff 28=3e0 F=80b80000
op 15 sf 0: 9=ffff8000 10=7fff 11=ffff8000 20=b3b04688 21=1000 22=7f00ff00 25=fff7f010 26=bf7e810 27=fff7f010 28=3e0 F=81f80000
op 16 sf 1: 9=fffffffe 10=407f 11=0 20=7f00ff00 21=7f00ff00 22=7f00ff00 25=fffffffe 26=407f 27=0 28=3e0 F=89f00000
op 16 sf 0: 9=ffff8000 10=7fff 11=ffff8000 20=7f00ff00 21=7f00ff00 22=7f00ff00 25=fff7f010 26=bf7e810 27=fff7f010 28=3e0 F=c9f80000
op 17 sf 1: 10=407f 11=0 20=7f00ff00 21=7f00ff00 22=7f00ff00 25=ffffffff 26=407f 27=0 28=3e0 F=89f00000
op 17 sf 0: 9=ffff8000 10=7fff 11=ffff8000 20=7fffff00 21=7fffff00 22=7f00ff00 25=fff7f010 26=bf7e810 27=fff7f010 28=3e0 F=c9f80000
op 18 sf 1: 9=fffffffe 10=7fff 11=ffffffff 20=7f00ff00 21=7f00ff00 22=7f00ff00 25=fffffffe 26=87ef 27=ffffffff 28=3e0 F=80b80000
op 18 sf 0: 9=ffff8000 10=7fff 11=ffff8000 20=7fffff00 21=7fffff00 22=7f00ff00 25=fffef010 26=87ef000 27=fff7f010 28=3e0 F=81f80000
op 19 sf 1: 9=fffffffe 10=7fff 11=ffffffff 20=1000 21=7f00ff00 22=7f00ff00 25=fffffffe 26=87ef 27=ffffffff 28=3e0 F=80b80000
op 19 sf 0: 9=ffff8000 10=7fff 11=ffff8000 20=1000 21=7fffff00 22=7f00ff00 25=fffef010 26=87ef000 27=fff7f010 28=3e0 F=81f80000
op 1A sf 1: 9=fffffffe 10=7fff 11=ffffffff 20=b3b04688 21=1000 22=7f00ff00 25=fffffffe 26=87ef 27=ffffffff 28=3e0 F=80b80000
op 1A sf 0: 9=ffff8000 10=7fff 11=ffff8000 20=b3b04688 21=1000 22=7f00ff00 25=fffef010 26=87ef000 27=fff7f010 28=3e0 F=81f80000
op 1B sf 1: 9=7f7f 10=ffffc080 11=ffff8080 20=b3b04688 21=1000 22=7f0000ff 25=7f7f 26=ffffc080 27=ffff8080 28=1f F=89f80000
op 1B sf 0: 9=7fff 10=7fff 20=b3b04688 21=1000 22=7fffffff 25=7f7f010 26=3f7f810 27=7f7f010 28=7fff F=c9f80000
op 1C sf 1: 9=ffff8080 10=ffffc080 11=ffff8080 20=b3b04688 21=1000 22=7f000000 25=ffff8080 26=ffffc080 27=ffff8080 28=0 F=81f80000
op 1C sf 0: 9=7fff 10=7fff 20=b3b04688 21=1000 22=7fffffff 25=7f7f010 26=3f7f810 27=7f7f010 28=7fff F=81f80000
op 1D sf 1: 9=7f7f 10=3f7f 11=7f7f 20=b3b04688 21=1000 22=7fffffff 25=7f7f 26=3f7f 27=7f7f 28=7fff F=380000
op 1D sf 0: 9=7fff 10=7fff 20=b3b04688 21=1000 22=7fffffff 25=7f7f010 26=3f7f810 27=7f7f010 28=7fff F=81f80000
op 1E sf 1: 9=7fff 10=ffff8000 11=ffff8000 20=b3b04688 21=1000 22=7f0000ff 25=7fffbc38 26=c6c54f47 27=91147f57 28=1f F=89f80000
op 1E sf 0: 9=7fff 10=7fff 20=b3b04688 21=1000 22=7fffffff 25=8008000 26=54f42001 27=11c8cc8d 28=7fff F=c9f80000
op 1F sf 1: 9=ffff8000 10=ffff8000 11=ffff8000 20=b3b04688 21=1000 22=7f000000 25=80008008 26=c6c54f42 27=91111c8c 28=0 F=c9f80000
op 1F sf 0: 9=7fff 10=7fff 20=b3b04688 21=1000 22=7fffffff 25=8008000 26=54f42001 27=11c8cc8d 28=7fff F=c9f80000
op 20 sf 1: 9=7fff 10=ffff8000 11=ffff8000 20=7f0000ff 21=7f0000ff 22=7f0000ff 25=7ffd9240 26=c6c54f44 27=9115b687 28=1f F=89f80000
op 20 sf 0: 9=7fff 10=7fff 20=7fffffff 21=7fffffff 22=7fffffff 25=8008000 26=54f42001 27=11c8cc8d 28=7fff F=c9f80000
op 21 sf 1: 9=ffff8000 10=ffff8000 11=ffff8000 20=7f000000 21=7f000000 22=7f000000 25=80000008 26=c6c54f39 27=9111a48f 28=0 F=c9f80000
op 21 sf 0: 9=7fff 10=7fff 20=7fffffff 21=7fffffff 22=7fffffff 25=8000 26=54f39001 27=1a48fc8d 28=7fff F=c9f80000
op 22 sf 1: 9=ffff8000 10=ffff8000 11=ffff8000 20=7f0000ff 21=7f000000 22=7f000000 25=80000008 26=c6c54f39 27=9111a48f 28=0 F=c9f80000
op 22 sf 0: 9=7fff 10=7fff 20=7fffff00 21=7fffffff 22=7fffffff 25=8000 26=54f39001 27=1a48fc8d 28=7fff F=c9f80000
op 23 sf 1: 9=ffff8000 10=ffff8000 11=ffff8000 20=7f002311 21=7f000000 22=7f000000 25=80000008 26=c6c54f39 27=9111a48f 28=0 F=c9f80000
op 23 sf 0: 9=7fff 10=7fff 20=7fff2311 21=7fffffff 22=7fffffff 25=8000 26=54f39001 27=1a48fc8d 28=7fff F=c9f80000
op 24 sf 1: 9=ffff8000 10=ffff8000 11=ffff8000 20=1000 21=7f000000 22=7f000000 25=80000008 26=c6c54f39 27=9111a48f 28=0 F=c9f80000
op 24 sf 0: 9=7fff 10=7fff 20=1000 21=7fffffff 22=7fffffff 25=8000 26=54f39001 27=1a48fc8d 28=7fff F=c9f80000
op 25 sf 1: 9=ffff8000 10=ffff8000 11=ffff8000 20=b3b04688 21=1000 22=7f000000 25=80000008 26=c6c54f39 27=9111a48f 28=0 F=81f80000
op 25 sf 0: 9=7fff 10=7fff 20=b3b04688 21=1000 22=7fffffff 25=8000 26=54f39001 27=1a48fc8d 28=7fff F=81f80000
op 26 sf 1: 10=ffff8000 11=ffff8000 20=b3b04688 21=1000 22=7f0000ff 26=c6c54f39 27=9111a48f 28=0 F=80d80000
op 26 sf 0: 10=7fff 20=b3b04688 21=1000 22=7fffffff 26=54f39001 27=1a48fc8d F=80d80000
op 27 sf 1: 11=ffff8000 20=b3b04688 21=1000 22=7f002311 27=9111a48f 28=3e0 F=480000
op 27 sf 0: 20=b3b04688 21=1000 22=7fff2311 27=1a48fc8d F=480000
op 28 sf 1: 9=0 25=0 26=1000 27=3fff0 F=400000
op 28 sf 0: 9=1 10=7fff 25=1 26=1000000 27=3fff0001 F=80c00000
op 29 sf 1: 9=fffffffe 10=7fff 11=ffffffff 20=b3b04688 21=1000 22=7f00ff00 25=fffffffe 26=87ef 27=ffffffff 28=3e0 F=80b80000
op 29 sf 0: 9=ffff8000 10=7fff 11=ffff8000 20=b3b04688 21=1000 22=7f00ff00 25=fffef010 26=87ef000 27=fff7f010 28=3e0 F=81f80000
op 2A sf 1: 10=7fff 11=0 20=7f00ff00 21=7f00ff00 22=7f00ff00 25=ffffffff 26=80ff 27=0 28=3e0 F=80b00000
op 2A sf 0: 9=ffff8000 10=7fff 11=0 20=7f00ff00 21=7f00ff00 22=7f00ff00 25=ff000000 26=80ff000 27=0 28=3e0 F=81f80000
op 2B sf 1: 10=7fff 11=0 21=7f00ff00 22=7f00ff00 25=ffffffff 26=80ff 27=0 28=3e0 F=80b00000
op 2B sf 0: 9=ffff8000 10=7fff 11=0 21=7f00ff00 22=7f00ff00 25=ff000000 26=80ff000 27=0 28=3e0 F=81f80000
op 2C sf 1: 10=7fff 11=0 22=7f00ff00 25=ffffffff 26=80ff 27=0 28=3e0 F=80b00000
op 2C sf 0: 9=ffff8000 10=7fff 11=0 22=7f00ff00 25=ff000000 26=80ff000 27=0 28=3e0 F=81b00000
op 2D sf 1: 7=0 24=ef21e181 F=80040000
op 2D sf 0: 7=0 24=ef21e181 F=80040000
op 2E sf 1: 7=0 24=c57ae939 F=80040000
op 2E sf 0: 7=0 24=c57ae939 F=80040000
op 2F sf 1: 7=0 9=7fff 10=7fff 20=7fffffff 21=7fffffff 22=7fffffff 24=dca18c84 25=8000 26=54f39001 27=1a48fc8d 28=7fff F=c9fc8000
op 2F sf 0: 7=0 9=7fff 10=7fff 20=7fffffff 21=7fffffff 22=7fffffff 24=45d48c84 25=8000 26=54f39001 27=1a48fc8d 28=7fff F=c9fc8000
op 30 sf 1: 8=0 9=ffff8000 10=7fff 11=ffff8000 12=3fffc00 13=3fffc00 14=3fffc00 16=c3a3 17=0 18=0 19=0 24=22632822 25=89c65e89 26=3b532619 27=8000c44b 28=3e0 F=81c7f000
op 30 sf 0: 8=0 9=7fff 10=7fff 12=3fffc00 13=3ff03ff 14=3ff03ff 16=c3a3 17=0 18=0 19=0 24=22632822 25=65e89000 26=32619148 27=c44b20b 28=7fff F=81c7f000
op 31 sf 1: 8=0 9=ffff8000 10=7fff 11=ffff8000 12=3fffc00 13=3fffc00 14=3fffc00 16=c3a3 17=0 18=0 19=0 24=22632822 25=89c65e89 26=3b532619 27=8000c44b 28=3e0 F=81c7f000
op 31 sf 0: 8=0 9=7fff 10=7fff 12=3fffc00 13=3ff03ff 14=3ff03ff 16=c3a3 17=0 18=0 19=0 24=22632822 25=65e89000 26=32619148 27=c44b20b 28=7fff F=81c7f000
op 32 sf 1: 8=0 9=ffff8000 10=7fff 11=ffff8000 12=3fffc00 13=3fffc00 14=3fffc00 16=c3a3 17=0 18=0 19=0 24=22632822 25=89c65e89 26=3b532619 27=8000c44b 28=3e0 F=81c7f000
op 32 sf 0: 8=0 9=7fff 10=7fff 12=3fffc00 13=3ff03ff 14=3ff03ff 16=c3a3 17=0 18=0 19=0 24=22632822 25=65e89000 26=32619148 27=c44b20b 28=7fff F=81c7f000
op 33 sf 1: 8=0 9=ffff8000 10=7fff 11=ffff8000 12=3fffc00 13=3fffc00 14=3fffc00 16=c3a3 17=0 18=0 19=0 24=22632822 25=89c65e89 26=3b532619 27=8000c44b 28=3e0 F=81c7f000
op 33 sf 0: 8=0 9=7fff 10=7fff 12=3fffc00 13=3ff03ff 14=3ff03ff 16=c3a3 17=0 18=0 19=0 24=22632822 25=65e89000 26=32619148 27=c44b20b 28=7fff F=81c7f000
op 34 sf 1: 8=0 9=ffff8000 10=7fff 11=ffff8000 12=3fffc00 13=3fffc00 14=3fffc00 16=e9f7 17=c3a3 18=0 19=0 24=22632822 25=89c65e89 26=3b532619 27=8000c44b 28=3e0 F=81c7f000
op 34 sf 0: 8=0 9=7fff 10=7fff 12=3fffc00 13=3ff03ff 14=3ff03ff 16=e9f7 17=c3a3 18=0 19=0 24=22632822 25=65e89000 26=32619148 27=c44b20b 28=7fff F=81c7f000
op 35 sf 1: 8=0 9=ffff8000 10=7fff 12=3fffc00 13=3fffc00 14=3ffff99 16=e9f7 17=c3a3 18=0 19=ffff 24=9b0151c0 25=89c65e89 26=3b532619 F=81c7f000
op 35 sf 0: 8=0 9=7fff 10=7fff 12=3ffff99 13=3ff03ff 14=3ff03ff 16=e9f7 17=c3a3 18=0 19=ffff 24=9b0151c0 25=65e89000 26=32619148 28=7fff F=81c77000
op 36 sf 1: 8=0 9=ffff8000 10=7fff 12=3ffff99 13=3ff03ff 14=3fffc00 16=29cd 17=e9f7 18=c3a3 19=0 24=22632822 25=89c65e89 26=3b532619 F=8183f000
op 36 sf 0: 8=0 9=7fff 10=7fff 12=3fffc00 13=3ff03ff 14=3ff03ff 16=29cd 17=e9f7 18=c3a3 19=0 24=22632822 25=65e89000 26=32619148 28=7fff F=8183f000
op 37 sf 1: 8=0 10=7fff 12=3fffc00 13=3ff03ff 14=3ff03ff 16=29cd 17=e9f7 18=c3a3 19=0 24=22632822 26=3b532619 F=8083f000
op 37 sf 0: 8=0 10=7fff 12=3fffc00 13=3ff03ff 14=3ff03ff 16=29cd 17=e9f7 18=c3a3 19=0 24=22632822 26=32619148 F=8083f000
op 38 sf 1: 8=0 10=7fff 12=3fffc00 13=3ff03ff 14=3ff03ff 16=29cd 17=e9f7 18=c3a3 19=0 24=22632822 26=3b532619 F=8083f000
op 38 sf 0: 8=0 10=7fff 12=3fffc00 13=3ff03ff 14=3ff03ff 16=29cd 17=e9f7 18=c3a3 19=0 24=22632822 26=32619148 F=8083f000
op 39 sf 1: 8=0 12=3fffc00 13=3ff03ff 14=3fffffe 16=29cd 17=e9f7 18=c3a3 19=0 24=22632822 F=8001f000
op 39 sf 0: 8=0 12=3fffc00 13=3ff03ff 14=3fffffe 16=29cd 17=e9f7 18=c3a3 19=0 24=22632822 F=8001f000
op 3A sf 1: 8=0 12=1000 13=3ff03ff 14=3fffffe 16=29cd 17=e9f7 18=c3a3 19=0 24=22632822 F=8001f000
op 3A sf 0: 8=0 12=1000 13=3ff03ff 14=3fffffe 16=29cd 17=e9f7 18=c3a3 19=0 24=22632822 F=8001f000
op 3B sf 1: 8=0 12=1000 14=3fffffe 24=22632822 F=8000b000
op 3B sf 0: 8=0 12=1000 14=3fffffe 24=22632822 F=8000b000
op 3C sf 1: 8=0 9=ffff8000 10=7fff 12=1000 14=3fffc00 16=29cd 17=e9f7 18=c3a3 19=0 24=22632822 25=cdadc000 26=42ced12c 27=14e522f2 F=81c7f000
op 3C sf 0: 8=0 9=ffff8000 10=7fff 12=1000 14=3fffc00 16=29cd 17=e9f7 18=c3a3 19=0 24=22632822 25=cdadc000 26=42ced12c 27=14e522f2 F=81c7f000
op 3D sf 1: 20=b3b04688 21=1000 22=7fffff00 25=ffffffff 26=1000 27=7fff F=380000
op 3D sf 0: 9=fffff000 10=7fff 20=b3b04688 21=1000 22=7fffff00 25=fffff000 26=1000000 27=7fff000 F=80f80000
op 3E sf 1: 9=7fff 10=ffff8000 20=b3b04688 21=1000 22=7fff00ff 25=53157f31 26=db67a9fc 27=43e637f3 28=7c1f F=81f80000
op 3E sf 0: 9=7fff 10=ffff8000 20=b3b04688 21=1000 22=7fff00ff 25=53156f32 26=dc6799fc 27=4be5a7f4 28=7c1f F=81f80000
op 3F sf 1: 9=7f7f 10=ffffc080 11=ffff8080 20=7f0000ff 21=7f0000ff 22=7f0000ff 25=7f7f 26=ffffc080 27=ffff8080 28=1f F=89f80000
op 3F sf 0: 9=7fff 10=7fff 20=7fffffff 21=7fffffff 22=7fffffff 25=7f7f010 26=3f7f810 27=7f7f010 28=7fff F=c9f80000
Done.

06FMD.txt

===== 06 FMD FU MDEC RESET COLOUR | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 800154CE
Reset timing: MDEC1 written 80000000h, then MDEC1 read eight times, each followed by
a timer 2 read (cycles since just before the write).
Idle, status after the reset write @ timer 2: 80040000@15 80040000@35 80040000@53 80040000@71 80040000@89 80040000@107 80040000@129 80040000@147
15 bit decode with the input full, nothing read, status after the reset write @ timer 2: E60400DF@15 80040000@35 80040000@53 80040000@71 80040000@99 80040000@117 80040000@135 80040000@153
Short decode counts by CPU (mdecout ODD's way): the 4bit/8bit block at 8 bit with its
tables, the step stream at 15 bit with its tables. Only `count` words are written.
8 bit, decode count 1, 1 words written: 48 words out, CRC A9DEB035, status 8204FFFF, first 8F9EA9AF last 118AFF72
8 bit, decode count 2, 2 words written: 32 words out, CRC F60B4B13, status 8204FFFF, first FFFB7B20 last 118AFF72
15 bit, decode count 4, 4 words written: 32 words out, CRC C2A8FA9D, status 8601FFFF, first 00000000 last 00000000
15 bit, decode count 5, 5 words written: 32 words out, CRC C2A8FA9D, status 8601FFFF, first 00000000 last 00000000
15 bit, decode count 6, 6 words written: 32 words out, CRC C2A8FA9D, status 8601FFFF, first 00000000 last 00000000
Colour matrix and clamp: one macroblock of DC-only blocks, Cr and Cb and all four Y as
given (10 bit DC values), quant table all 4, the standard scale table, unsigned, by CPU.
The first output word of each 8x8 quadrant at 24 bit and at 15 bit.
Cr -256 Cb -256 Y 0: 24 bit 192 words, 0000FF00 0000FF00 0000FF00 0000FF00; 15 bit 128 words, 03E003E0 03E003E0 03E003E0 03E003E0
Cr -256 Cb -64 Y 0: 24 bit 192 words, 0047E700 0047E700 0047E700 0047E700; 15 bit 128 words, 27A027A0 27A027A0 27A027A0 27A027A0
Cr -256 Cb 0 Y 0: 24 bit 192 words, 0080DC00 0080DC00 0080DC00 0080DC00; 15 bit 128 words, 43604360 43604360 43604360 43604360
Cr -256 Cb 64 Y 0: 24 bit 192 words, 00B9D100 00B9D100 00B9D100 00B9D100; 15 bit 128 words, 5F405F40 5F405F40 5F405F40 5F405F40
Cr -256 Cb 255 Y 0: 24 bit 192 words, 00FFB000 00FFB000 00FFB000 00FFB000; 15 bit 128 words, 7EC07EC0 7EC07EC0 7EC07EC0 7EC07EC0
Cr -64 Cb -256 Y 0: 24 bit 192 words, 5300C353 5300C353 5300C353 5300C353; 15 bit 128 words, 030A030A 030A030A 030A030A 030A030A
Cr -64 Cb -64 Y 0: 24 bit 192 words, 5347A253 5347A253 5347A253 5347A253; 15 bit 128 words, 268A268A 268A268A 268A268A 268A268A
Cr -64 Cb 0 Y 0: 24 bit 192 words, 53809753 53809753 53809753 53809753; 15 bit 128 words, 426A426A 426A426A 426A426A 426A426A
Cr -64 Cb 64 Y 0: 24 bit 192 words, 53B98C53 53B98C53 53B98C53 53B98C53; 15 bit 128 words, 5E2A5E2A 5E2A5E2A 5E2A5E2A 5E2A5E2A
Cr -64 Cb 255 Y 0: 24 bit 192 words, 53FF6B53 53FF6B53 53FF6B53 53FF6B53; 15 bit 128 words, 7DAA7DAA 7DAA7DAA 7DAA7DAA 7DAA7DAA
Cr 0 Cb -256 Y 0: 24 bit 192 words, 8000AC80 8000AC80 8000AC80 8000AC80; 15 bit 128 words, 02D002D0 02D002D0 02D002D0 02D002D0
Cr 0 Cb -64 Y 0: 24 bit 192 words, 80478B80 80478B80 80478B80 80478B80; 15 bit 128 words, 26302630 26302630 26302630 26302630
Cr 0 Cb 0 Y 0: 24 bit 192 words, 80808080 80808080 80808080 80808080; 15 bit 128 words, 42104210 42104210 42104210 42104210
Cr 0 Cb 64 Y 0: 24 bit 192 words, 80B97580 80B97580 80B97580 80B97580; 15 bit 128 words, 5DF05DF0 5DF05DF0 5DF05DF0 5DF05DF0
Cr 0 Cb 255 Y 0: 24 bit 192 words, 80FF5480 80FF5480 80FF5480 80FF5480; 15 bit 128 words, 7D707D70 7D707D70 7D707D70 7D707D70
Cr 64 Cb -256 Y 0: 24 bit 192 words, AD0095AD AD0095AD AD0095AD AD0095AD; 15 bit 128 words, 02760276 02760276 02760276 02760276
Cr 64 Cb -64 Y 0: 24 bit 192 words, AD4774AD AD4774AD AD4774AD AD4774AD; 15 bit 128 words, 25F625F6 25F625F6 25F625F6 25F625F6
Cr 64 Cb 0 Y 0: 24 bit 192 words, AD8069AD AD8069AD AD8069AD AD8069AD; 15 bit 128 words, 41B641B6 41B641B6 41B641B6 41B641B6
Cr 64 Cb 64 Y 0: 24 bit 192 words, ADB95EAD ADB95EAD ADB95EAD ADB95EAD; 15 bit 128 words, 5D965D96 5D965D96 5D965D96 5D965D96
Cr 64 Cb 255 Y 0: 24 bit 192 words, ADFF3DAD ADFF3DAD ADFF3DAD ADFF3DAD; 15 bit 128 words, 7D167D16 7D167D16 7D167D16 7D167D16
Cr 255 Cb -256 Y 0: 24 bit 192 words, FF0051FF FF0051FF FF0051FF FF0051FF; 15 bit 128 words, 015F015F 015F015F 015F015F 015F015F
Cr 255 Cb -64 Y 0: 24 bit 192 words, FF4730FF FF4730FF FF4730FF FF4730FF; 15 bit 128 words, 24DF24DF 24DF24DF 24DF24DF 24DF24DF
Cr 255 Cb 0 Y 0: 24 bit 192 words, FF8025FF FF8025FF FF8025FF FF8025FF; 15 bit 128 words, 40BF40BF 40BF40BF 40BF40BF 40BF40BF
Cr 255 Cb 64 Y 0: 24 bit 192 words, FFB91AFF FFB91AFF FFB91AFF FFB91AFF; 15 bit 128 words, 5C7F5C7F 5C7F5C7F 5C7F5C7F 5C7F5C7F
Cr 255 Cb 255 Y 0: 24 bit 192 words, FFFF00FF FFFF00FF FFFF00FF FFFF00FF; 15 bit 128 words, 7C1F7C1F 7C1F7C1F 7C1F7C1F 7C1F7C1F
Cr -256 Cb -256 Y -128: 24 bit 192 words, 00FFC800 00FFC800 00FFC800 00FFC800; 15 bit 128 words, 7F207F20 7F207F20 7F207F20 7F207F20
Cr -256 Cb -256 Y 127: 24 bit 192 words, 0C00FF0C 0C00FF0C 0C00FF0C 0C00FF0C; 15 bit 128 words, 03E103E1 03E103E1 03E103E1 03E103E1
Cr -256 Cb 255 Y -128: 24 bit 192 words, 00FF7000 00FF7000 00FF7000 00FF7000; 15 bit 128 words, 7DC07DC0 7DC07DC0 7DC07DC0 7DC07DC0
Cr -256 Cb 255 Y 127: 24 bit 192 words, 0C00EF0C 0C00EF0C 0C00EF0C 0C00EF0C; 15 bit 128 words, 03C103C1 03C103C1 03C103C1 03C103C1
Cr 255 Cb -256 Y -128: 24 bit 192 words, F2FF11F2 F2FF11F2 F2FF11F2 F2FF11F2; 15 bit 128 words, 7C5E7C5E 7C5E7C5E 7C5E7C5E 7C5E7C5E
Cr 255 Cb -256 Y 127: 24 bit 192 words, FF0090FF FF0090FF FF0090FF FF0090FF; 15 bit 128 words, 025F025F 025F025F 025F025F 025F025F
Cr 255 Cb 255 Y -128: 24 bit 192 words, F2FF00F2 F2FF00F2 F2FF00F2 F2FF00F2; 15 bit 128 words, 7C1E7C1E 7C1E7C1E 7C1E7C1E 7C1E7C1E
Cr 255 Cb 255 Y 127: 24 bit 192 words, FF0038FF FF0038FF FF0038FF FF0038FF; 15 bit 128 words, 00FF00FF 00FF00FF 00FF00FF 00FF00FF
Cr 0 Cb 0 Y -128: 24 bit 192 words, 40404040 40404040 40404040 40404040; 15 bit 128 words, 21082108 21082108 21082108 21082108
Cr 0 Cb 0 Y 127: 24 bit 192 words, BFBFBFBF BFBFBFBF BFBFBFBF BFBFBFBF; 15 bit 128 words, 63186318 63186318 63186318 63186318
Cr 64 Cb -64 Y -128: 24 bit 192 words, 6D07346D 6D07346D 6D07346D 6D07346D; 15 bit 128 words, 04EE04EE 04EE04EE 04EE04EE 04EE04EE
Cr 64 Cb -64 Y 127: 24 bit 192 words, EC86B3EC EC86B3EC EC86B3EC EC86B3EC; 15 bit 128 words, 46DD46DD 46DD46DD 46DD46DD 46DD46DD
Cr -64 Cb 64 Y -128: 24 bit 192 words, 13794C13 13794C13 13794C13 13794C13; 15 bit 128 words, 3D223D22 3D223D22 3D223D22 3D223D22
Cr -64 Cb 64 Y 127: 24 bit 192 words, 92F8CB92 92F8CB92 92F8CB92 92F8CB92; 15 bit 128 words, 7F327F32 7F327F32 7F327F32 7F327F32
Done.

07FSP.txt

===== 07 FSP FU SPU ENV FIFO | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 800154CE
Envelope counter, one for all voices or one each: voices 0 and 1 attack linear shift
16 step 0, keyed on 1500 cycles apart; cycles from voice 0's KON.
Voice 0 keyed on at 0, voice 1 at 1646; first level changes, voice 0: 17918 42486 67054 91702; voice 1: 17918 42486 67054 91702; levels then 002A 002A
Voice 0 keyed on at 0, voice 1 at 1597; first level changes, voice 0: 17800 42352 66928 91576; voice 1: 17800 42352 66928 91576; levels then 002A 002A
Voice 0 keyed on at 0, voice 1 at 1597; first level changes, voice 0: 17889 42441 67000 91553; voice 1: 17889 42441 67000 91553; levels then 002A 002A
ADSR level times the sample: tone T on voice 1, pitch 1000h, held at 7FFFh; the level
register written, then the voice 1 capture buffer (first 16 samples).
Level as it stands, 255 changes in 256:
  014C 01B7 021B 0278 02D0 0322 036F 0392 02FE 024F 01AA 010F 007E FFF7 FF78 FF01
Level read 3FFF
Level written 4000h, reads 4000
Level 4000h, 255 changes in 256:
  02FF 024F 01AA 0110 007F FFF7 FF78 FF01 FE91 FE29 FDC7 FD6A FD14 FD4A FF98 007F
Level written 7FFFh, reads 7FFF
Level 7FFFh, 255 changes in 256:
  FD23 FC53 FB8E FAD5 FA29 FA94 FF31 00FD 01FC 02FB 03FA 04F9 05F8 0497 FA60 F907
FIFO drain: halfwords B000h, B001h, .. to scratch at 30000h (filled EEEEh) by one DMA
block of 16 words, a wait, SPUCNT transfer mode Stop, then read back by DMA.
Wait 0 cycles after the DMA ended: 9 of 32 halfwords written, 16 still EEEEh, first B000 last EEEE
Wait 100 cycles after the DMA ended: 10 of 32 halfwords written, 16 still EEEEh, first B000 last EEEE
Wait 200 cycles after the DMA ended: 10 of 32 halfwords written, 16 still EEEEh, first B000 last EEEE
Wait 300 cycles after the DMA ended: 14 of 32 halfwords written, 16 still EEEEh, first B000 last EEEE
Wait 400 cycles after the DMA ended: 18 of 32 halfwords written, 14 still EEEEh, first B000 last EEEE
Wait 500 cycles after the DMA ended: 22 of 32 halfwords written, 10 still EEEEh, first B000 last EEEE
Wait 600 cycles after the DMA ended: 26 of 32 halfwords written, 6 still EEEEh, first B000 last EEEE
Wait 700 cycles after the DMA ended: 31 of 32 halfwords written, 1 still EEEEh, first B000 last EEEE
Wait 800 cycles after the DMA ended: 32 of 32 halfwords written, 0 still EEEEh, first B000 last B01F
Wait 900 cycles after the DMA ended: 32 of 32 halfwords written, 0 still EEEEh, first B000 last B01F
Wait 1000 cycles after the DMA ended: 32 of 32 halfwords written, 0 still EEEEh, first B000 last B01F
Wait 1100 cycles after the DMA ended: 32 of 32 halfwords written, 0 still EEEEh, first B000 last B01F
Wait 1200 cycles after the DMA ended: 32 of 32 halfwords written, 0 still EEEEh, first B000 last B01F
Wait 1300 cycles after the DMA ended: 32 of 32 halfwords written, 0 still EEEEh, first B000 last B01F
Wait 1400 cycles after the DMA ended: 32 of 32 halfwords written, 0 still EEEEh, first B000 last B01F
Wait 1500 cycles after the DMA ended: 32 of 32 halfwords written, 0 still EEEEh, first B000 last B01F
Wait 1600 cycles after the DMA ended: 32 of 32 halfwords written, 0 still EEEEh, first B000 last B01F
Start address one 8 byte unit past a block (spuenv END's S4+8 case): tone T on voice 1,
pitch 1000h, start and repeat as given; the voice 1 capture buffer.
Start 40C0h (the block), 65 changes in 256:
  0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
  0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
Start 40C1h (one unit in), 255 changes in 256:
  FDC7 FD6A FD14 FD4A FF98 007E 00FE 017D 01FD 027C 02FC 024B FD30 FC83 FD03 FD82
  FE01 FE81 FF00 FF80 FFFF 007E 00FE 017D 01FD 027C 02FC 024B FD30 FC83 FD03 FD88
Done.

08FDS.txt

===== 08 FDS FU DMA SPU BLOCKS | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 800154CE
DMA4 SPU write SyncMode 1, 256 words to 30000h, cycles from the CHCR write until bit 24
clears, three times each. SPU delay register (1F801014h) was 200931E1.
Delay 200931E1, blocks of 1 words x 256: 16350 16375 16372
Delay 200931E1, blocks of 2 words x 128: 16320 16320 16320
Delay 200931E1, blocks of 4 words x 64: 18264 18272 18272
Delay 200931E1, blocks of 8 words x 32: 17077 17085 17085
Delay 200931E1, blocks of 16 words x 16: 16843 16843 16843
Delay 200931E1, blocks of 32 words x 8: 8574 8508 8555
Delay 210931E1, blocks of 1 words x 256: 16383 16374 16374
Delay 210931E1, blocks of 2 words x 128: 17044 17042 17042
Delay 210931E1, blocks of 4 words x 64: 18300 18290 18290
Delay 210931E1, blocks of 8 words x 32: 17861 17867 17867
Delay 210931E1, blocks of 16 words x 16: 17550 17256 17258
Delay 210931E1, blocks of 32 words x 8: 8620 8570 8582
Delay 220931E1, blocks of 1 words x 256: 16340 16366 16342
Delay 220931E1, blocks of 2 words x 128: 19587 19585 19585
Delay 220931E1, blocks of 4 words x 64: 18318 18285 18285
Delay 220931E1, blocks of 8 words x 32: 18654 18629 18629
Delay 220931E1, blocks of 16 words x 16: 17784 17720 17782
Delay 220931E1, blocks of 32 words x 8: 9488 9457 9467
Delay 230931E1, blocks of 1 words x 256: 17864 17866 17866
Delay 230931E1, blocks of 2 words x 128: 19568 19568 19568
Delay 230931E1, blocks of 4 words x 64: 19437 19467 19465
Delay 230931E1, blocks of 8 words x 32: 18643 18633 18633
Delay 230931E1, blocks of 16 words x 16: 17816 17814 17814
Delay 230931E1, blocks of 32 words x 8: 10203 10188 10188
SPU delay register back to 200931E1
Done.

09FSI.txt

===== 09 FSI FU SIO RXEN IMASK | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 800154CE
Controller port with RXEN and no device selected (JOY_CTRL bit 1 clear), slot 1.
CTRL 0004, no data written; JOY_STAT (bits 0-10) every 100 cycles from 0 to 3000:
  005 005 005 005 005 005 005 005 005 005 005 005 005 005 007 007 007 007 007 007 007 007 007 007 007 007 007 007 007 007 007
  bytes in the RX FIFO: 1 FF; I_STAT bit 7 then 0
CTRL 0805, no data written; JOY_STAT (bits 0-10) every 100 cycles from 0 to 3000:
  005 005 005 005 005 005 005 005 005 005 005 005 005 005 207 207 207 207 207 207 207 207 207 207 207 207 207 207 207 207 207
  bytes in the RX FIFO: 1 FF; I_STAT bit 7 then 1
I_MASK's upper half (the console read 960507FFh after sw FFFFFFFFh, chainb/028/01IMR.txt:4):
sw 12345678h to I_MASK, lw at once: AD090678
sw 12345678h, lui/ori of CAFEBABEh, then lw: AD090678
sw 12345678h, lw of I_STAT and a nop, then lw: AE020678
I_MASK back to 00000009
Done.

10FGR.txt

===== 10 FGR FU GPU RASTER | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 800154CE
GPU: the drawing offset's wrap, GP1(10h) upper bits, the C0h pad, two CLUT rows, and
last the time 42 unwaited GP0 stores take.
GPUSTAT 5606200F at the start
Tile 60h 16x1 red, drawing area x 64..95 on row 420:
Offset 0, vertex x 76 (the setup, no wrap): 16 of 32 drawn in x 64..95, first at x 76
  ............################....
Offset 500, vertex x 600 (sum 1100): 0 of 32 drawn in x 64..95
  ................................
Offset 1000, vertex x 100 (sum 1100): 0 of 32 drawn in x 64..95
  ................................
GP1(10h), whole words:
E1 0 (4 bit page at 0,0): E2 FFFFFFh, then index 2 five times: 000FFFFF 000FFFFF 000FFFFF 000FFFFF 000FFFFF; after reading 4 pixels (1230 1231 1232 1233): 123FFFFF
  E3 FFFFFFh, then index 3 five times: 123FFFFF 123FFFFF 123FFFFF 123FFFFF 123FFFFF; after reading the pixels again: 123FFFFF
E1 4 bit page at 512,256: E2 FFFFFFh, then index 2 five times: 123FFFFF 123FFFFF 123FFFFF 123FFFFF 123FFFFF; after reading 4 pixels (1230 1231 1232 1233): 123FFFFF
  E3 FFFFFFh, then index 3 five times: 123FFFFF 123FFFFF 123FFFFF 123FFFFF 123FFFFF; after reading the pixels again: 123FFFFF
E1 15 bit page at 768,256: E2 FFFFFFh, then index 2 five times: 123FFFFF 123FFFFF 123FFFFF 123FFFFF 123FFFFF; after reading 4 pixels (1230 1231 1232 1233): 123FFFFF
  E3 FFFFFFh, then index 3 five times: 123FFFFF 123FFFFF 123FFFFF 123FFFFF 123FFFFF; after reading the pixels again: 123FFFFF
GP0(C0h) pad halfword:
Row 408 all 2222h, row 409 all 3333h: C0h 3x1 at 100,408 reads 22222222 22222222; GPUSTAT then 56062000
Row 408 2220h, 2221h, .. 2227h, row 409 all 3333h: C0h 3x1 at 100,408 reads 22212220 22232222; GPUSTAT then 56062000
CLUT rows of gpuraster CLC, 256x1 sprites of row v 1 of the page at 576,256, CLUT at
256,y holding 4000h|i; texture cache cleared first:
15 bit mode (E1 depth 2), first 16 pixels: 0100 0302 0504 0706 0908 0B0A 0D0C 0F0E 1110 1312 1514 1716 1918 1B1A 1D1C 1F1E
Depth 3 (E1 bits 7-8 = 3), first 16 pixels: 0100 0302 0504 0706 0908 0B0A 0D0C 0F0E 1110 1312 1514 1716 1918 1B1A 1D1C 1F1E
8 bit, CLUT row overwritten with 7FFFh, second sprite with CLUT x 272 (+16), pixels 240..255: 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
  its pixels 0..15: 7FFF 7FFF 7FFF 7FFF 7FFF 7FFF 7FFF 7FFF 7FFF 7FFF 7FFF 7FFF 7FFF 7FFF 7FFF 7FFF
The zigzag polyline of 40 vertices, 42 GP0 stores with no wait: not run in this table.
Waits that ran out: 0
Done.

11FCD.txt

===== 11 FCD FU CD NO DISC | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 800154CE
CD-ROM, no disc: parameters left by an invalid command, Init's mode, Reset's deaf
window (last). Times are cycles from the command's write.
Switches (Test 21h, bit1 door open, bit0 head at POS0): int3 03 @28313. Getstat: int3 10 @28440. Mode 20. HINTMSK was 1F.
2 parameters then command 40h: int5 11 40 @21392; HSTS after its acknowledge 11; 0 cycles later HSTS 11; Getstat: int5 11 20 @33599
2 parameters then command 40h: int5 11 40 @19272; HSTS after its acknowledge 11; 10000 cycles later HSTS 11; Getstat: int5 11 20 @33023
2 parameters then command 40h: int5 11 40 @23652; HSTS after its acknowledge 11; 100000 cycles later HSTS 11; Getstat: int5 11 20 @32837
Init (0Ah): int3 10 @53114 | int2 10 @78154; Getparam then gives mode 20
Reset (1Ch), then a Getstat: not run in this table.
Reset (1Ch), then a Getstat: not run in this table.
Reset (1Ch), then a Getstat: not run in this table.
Reset (1Ch), then a Getstat: not run in this table.
Reset (1Ch), then a Getstat: not run in this table.
Reset (1Ch), then a Getstat: not run in this table.
Done.

28 September 2026

00RUN.txt

===== 00 RUN | BIOS 19951204 System ROM Version 3.0 11/18/96 A
11 tests
A chain program, linked at 80100000
Saved on the card in slot 2, from image 1
COP0 at start: BPC 00000000 BDA 80024F50 TAR BFC02BAC DCIC 00000000 BadVaddr 800154CE BDAM FFFFFFFF
BPCM 00000000 SR 40000000 Cause 00000020 EPC 80021B7C PRId 00000002

01FTS.txt

===== 01 FTS FU TIMER2 STOPPED | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 800154CE
Timer2 stopped (mode 0001h: sync on, sync mode 0). Each row: the target written, mode
0001h written and read once, the counter written, 500 cycles, then the mode read once.
Bit 11 (0800h) is reached target, bit 12 (1000h) reached FFFFh.
Target 8000, counter written 1234: mode reads 0401, counter reads 1234
Target 8000, counter written 7FFF: mode reads 0401, counter reads 7FFF
Target 8000, counter written 8000: mode reads 0C01, counter reads 8000
Target 8000, counter written 8001: mode reads 0401, counter reads 8001
Target 8000, counter written FFFF: mode reads 0401, counter reads FFFF
Target 8000, counter written 0000: mode reads 0401, counter reads 0000
Target 1234, counter written 1234: mode reads 0C01, counter reads 1234
Target 1234, counter written 1233: mode reads 0401, counter reads 1233
Done.

02FTM.txt

===== 02 FTM FU TIMER MODE READS | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 800154CE
Timer0 system clock, mode 0000 written then the counter read at once, 8 times: 0 0 0 0 0 0 0 0
Timer1 system clock, mode 0000 written then the counter read at once, 8 times: 0 0 0 0 0 0 0 0
Timer2 system clock, mode 0000 written then the counter read at once, 8 times: 0 0 0 0 0 0 0 0
Timer1 hblank clock, mode 0100 written then the counter read at once, 8 times: 0 0 0 0 0 0 0 0
Timer0 dotclock, mode 0100 written then the counter read at once, 8 times: 0 0 0 0 0 0 0 0
Done.

03FVB.txt

===== 03 FVB FU T1 VBLANK EDGE | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 800154CE
Timer1 sync mode 1 (reset at vblank), set at the vblank IRQ (I_STAT bit 0); timer 2
counts system cycles from then. Where timer 1 first reads lower than before is the reset.
Timer1 system clock, sync mode 1 (mode 0003h):
  Timer1 read 49428 then 24 at 49459 cycles after the vblank IRQ (the read before at 49418)
  Timer1 read 49451 then 33 at 49496 cycles after the vblank IRQ (the read before at 49455)
  Timer1 read 49453 then 32 at 49498 cycles after the vblank IRQ (the read before at 49457)
  Timer1 read 49453 then 32 at 49498 cycles after the vblank IRQ (the read before at 49457)
Timer1 hblank clock, sync mode 1 (mode 0103h):
  Timer1 read 24 then 0 at 52032 cycles after the vblank IRQ (the read before at 51991)
  Timer1 read 24 then 0 at 52040 cycles after the vblank IRQ (the read before at 51999)
  Timer1 read 24 then 0 at 52035 cycles after the vblank IRQ (the read before at 51994)
  Timer1 read 24 then 0 at 52040 cycles after the vblank IRQ (the read before at 51999)
Timer1 hblank clock free run (mode 0100h) zeroed at one vblank IRQ, read at the next: 263 263 263 263
Done.

04FDI.txt

===== 04 FDI FU DICR LATENCY | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 800154CE
IRQ3 masked in I_MASK, interrupts off. DICR written, then eight loads of I_STAT, each
followed by a load of timer 2.
DICR 00000000 written; then I_STAT bit 3 and timer 2 (cycles since just before the write): 0@15 0@36 0@72 0@93 0@129 0@150 0@186 0@207
DICR 00008000 written; then I_STAT bit 3 and timer 2 (cycles since just before the write): 0@5 1@25 1@59 1@80 1@116 1@137 1@173 1@191
DICR 00008000 written; then I_STAT bit 3 and timer 2 (cycles since just before the write): 0@5 1@27 1@61 1@82 1@118 1@139 1@175 1@193
DICR 00008000 written; then I_STAT bit 3 and timer 2 (cycles since just before the write): 0@5 1@23 1@57 1@78 1@114 1@135 1@171 1@189
DICR was 00000000 and is back to 0, then its enables.
Done.

05FGT.txt

===== 05 FGT FU GTE IR0 OPCODES | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 800154CE
IR0 at the edge (the gteres RTPS inputs, V0 100h,100h,10h, DQA 0):
RTPS sf 1, DQA 0, DQB 1000000: IR0 1000, MAC0 1000000, FLAG 00000000; changed: 8=1000 9=166 10=a1 11=803 14=a000f9 19=803 24=1000000 25=166 26=a1 27=803 28=4022 F=0
RTPS sf 1, DQA 0, DQB 0FFFFFF: IR0 FFF, MAC0 FFFFFF, FLAG 00000000; changed: 8=fff 9=166 10=a1 11=803 14=a000f9 19=803 24=ffffff 25=166 26=a1 27=803 28=4022 F=0
RTPS sf 1, DQA 0, DQB 1000FFF: IR0 1000, MAC0 1000FFF, FLAG 00001000; changed: 8=1000 9=166 10=a1 11=803 14=a000f9 19=803 24=1000fff 25=166 26=a1 27=803 28=4022 F=1000
Every opcode 00h-3Fh with sf 1 and sf 0, lm 0, no other bits, each on the same seeded
inputs as gteres GNA (seed 5501AA00, SXYP IRGB ORGB LZCR not written); the registers
the command changed as <register>=<hex> (0-31 data, 32-63 control), then F=FLAG:
op 00 sf 1: 8=0 9=ffff8000 10=7fff 11=ffff8000 12=1000 14=3fffc00 16=29cd 17=e9f7 18=c3a3 19=0 24=22632822 25=89bcdadc 26=3b542ced 27=80014e52 28=3e0 F=81c7f000
op 00 sf 0: 8=0 9=ffff8000 10=7fff 12=1000 14=3fffc00 16=29cd 17=e9f7 18=c3a3 19=0 24=22632822 25=cdadc000 26=42ced12c 27=14e522f2 F=81c7f000
op 01 sf 1: 8=0 9=ffff8000 10=7fff 11=ffff8000 12=1000 14=3fffc00 16=29cd 17=e9f7 18=c3a3 19=0 24=22632822 25=89bcdadc 26=3b542ced 27=80014e52 28=3e0 F=81c7f000
op 01 sf 0: 8=0 9=ffff8000 10=7fff 12=1000 14=3fffc00 16=29cd 17=e9f7 18=c3a3 19=0 24=22632822 25=cdadc000 26=42ced12c 27=14e522f2 F=81c7f000
op 02 sf 1: 8=0 9=ffff8000 10=7fff 12=1000 14=3fffc00 16=29cd 17=e9f7 18=c3a3 19=0 24=22632822 25=89bcdadc 26=3b542ced F=81c7f000
op 02 sf 0: 8=0 9=ffff8000 10=7fff 12=1000 14=3fffc00 16=29cd 17=e9f7 18=c3a3 19=0 24=22632822 25=cdadc000 26=42ced12c F=81c7f000
op 03 sf 1: 8=0 10=7fff 12=1000 14=3ff03ff 16=29cd 17=e9f7 18=c3a3 19=0 24=22632822 26=3b542ced F=8083f000
op 03 sf 0: 8=0 10=7fff 12=1000 14=3ff03ff 16=29cd 17=e9f7 18=c3a3 19=0 24=22632822 26=42ced12c F=8083f000
op 04 sf 1: 8=0 12=1000 14=3fffffe 24=22632822 F=8000b000
op 04 sf 0: 8=0 12=1000 14=3fffffe 24=22632822 F=8000b000
op 05 sf 1: 8=0 9=ffff8000 10=7fff 12=1000 14=3fffc00 16=29cd 17=e9f7 18=c3a3 19=0 24=22632822 25=cdadc000 26=42ced12c 27=14e522f2 F=81c7f000
op 05 sf 0: 8=0 9=ffff8000 10=7fff 12=1000 14=3fffc00 16=29cd 17=e9f7 18=c3a3 19=0 24=22632822 25=cdadc000 26=42ced12c 27=14e522f2 F=81c7f000
op 06 sf 1: 24=0 F=0
op 06 sf 0: 24=0 F=0
op 07 sf 1: 24=74087000 F=80008000
op 07 sf 0: 24=f4086fff F=0
op 08 sf 1: 24=c4086fff F=0
op 08 sf 0: 24=f5087000 F=0
op 09 sf 1: 24=dc086fff F=0
op 09 sf 0: 24=dc086fff F=0
op 0A sf 1: 24=c057394e F=0
op 0A sf 0: 24=f157394f F=0
op 0B sf 1: 9=7fff 10=7fff 20=7fffffff 21=7fffffff 22=7fffffff 24=efffffff 25=8000 26=54f39001 27=1a48fc8d 28=7fff F=81f80000
op 0B sf 0: 9=7fff 10=7fff 20=7fffffff 21=7fffffff 22=7fffffff 24=d7ffffff 25=8000 26=54f39001 27=1a48fc8d 28=7fff F=81f80000
op 0C sf 1: 9=2fcf 10=7fff 11=ffff8001 25=2fcf 26=3fff0 27=ffff8001 28=3ff F=80800000
op 0C sf 0: 9=7fff 10=7fff 11=ffff8000 25=2fcfa06 26=3fff0001 27=f80015fa 28=3ff F=81c00000
op 0D sf 1: 9=ffff8000 10=7fff 11=ffff8001 25=fffd0000 26=3fff0 27=ffff8001 28=3e0 F=81800000
op 0D sf 0: 9=ffff8000 10=7fff 11=ffff8000 25=c8000fff 26=3fff0001 27=f80015fa 28=3e0 F=81c00000
op 0E sf 1: 10=7fff 11=1 26=7fff0 27=1 28=3e0 F=80800000
op 0E sf 0: 10=ffff8000 11=15f9 26=8afb0001 27=15f9 28=7c00 F=80800000
op 0F sf 1: 9=7fff 10=7fff 20=7fffffff 21=7fffffff 22=7fffffff 25=48008000 26=54f42001 27=48d4c8d 28=7fff F=81f80000
op 0F sf 0: 9=7fff 10=7fff 20=7fffffff 21=7fffffff 22=7fffffff 25=48008000 26=54f42001 27=48d4c8d 28=7fff F=81f80000
op 10 sf 1: 10=7fff 11=0 20=b3b04688 21=1000 22=7f00ff00 25=ffffffff 26=87ef 27=0 28=3e0 F=80b00000
op 10 sf 0: 9=ffff8000 10=7fff 11=ffff8000 20=b3b04688 21=1000 22=7f00ff00 25=f8ff0000 26=87ef000 27=f8ff0000 28=3e0 F=81f80000
op 11 sf 1: 10=7fff 11=0 20=b3b04688 21=1000 22=7f00ff00 25=ffffffff 26=8fff 27=0 28=3e0 F=80b00000
op 11 sf 0: 9=fffff000 10=7fff 11=fffff000 20=b3b04688 21=1000 22=7f00ff00 25=fffff000 26=8fff000 27=fffff000 28=3e0 F=80f80000
op 12 sf 1: 9=ffff8000 10=7fff 11=ffff8000 25=89bcdadc 26=3b542ced 27=80014e52 28=3e0 F=81c00000
op 12 sf 0: 9=ffff8000 10=7fff 25=cdadc000 26=42ced12c 27=14e522f2 F=81c00000
op 13 sf 1: 9=fffffffe 10=407f 11=0 20=b3b04688 21=1000 22=7f00ff00 25=fffffffe 26=407f 27=0 28=3e0 F=89f00000
op 13 sf 0: 9=ffff8000 10=7fff 11=ffff8000 20=b3b04688 21=1000 22=7f00ff00 25=fff7f010 26=bf7e810 27=fff7f010 28=3e0 F=c9f80000
op 14 sf 1: 10=407f 11=0 20=b3b04688 21=1000 22=7f00ff00 25=ffffffff 26=407f 27=0 28=3e0 F=81f00000
op 14 sf 0: 9=ffff8000 10=7fff 11=ffff8000 20=b3b04688 21=1000 22=7f00ff00 25=fff7f010 26=bf7e810 27=fff7f010 28=3e0 F=81f80000
op 15 sf 1: 9=fffffffe 10=7fff 11=ffffffff 20=b3b04688 21=1000 22=7f00ff00 25=fffffffe 26=bf7e 27=ffffffff 28=3e0 F=80b80000
op 15 sf 0: 9=ffff8000 10=7fff 11=ffff8000 20=b3b04688 21=1000 22=7f00ff00 25=fff7f010 26=bf7e810 27=fff7f010 28=3e0 F=81f80000
op 16 sf 1: 9=fffffffe 10=407f 11=0 20=7f00ff00 21=7f00ff00 22=7f00ff00 25=fffffffe 26=407f 27=0 28=3e0 F=89f00000
op 16 sf 0: 9=ffff8000 10=7fff 11=ffff8000 20=7f00ff00 21=7f00ff00 22=7f00ff00 25=fff7f010 26=bf7e810 27=fff7f010 28=3e0 F=c9f80000
op 17 sf 1: 10=407f 11=0 20=7f00ff00 21=7f00ff00 22=7f00ff00 25=ffffffff 26=407f 27=0 28=3e0 F=89f00000
op 17 sf 0: 9=ffff8000 10=7fff 11=ffff8000 20=7fffff00 21=7fffff00 22=7f00ff00 25=fff7f010 26=bf7e810 27=fff7f010 28=3e0 F=c9f80000
op 18 sf 1: 9=fffffffe 10=7fff 11=ffffffff 20=7f00ff00 21=7f00ff00 22=7f00ff00 25=fffffffe 26=87ef 27=ffffffff 28=3e0 F=80b80000
op 18 sf 0: 9=ffff8000 10=7fff 11=ffff8000 20=7fffff00 21=7fffff00 22=7f00ff00 25=fffef010 26=87ef000 27=fff7f010 28=3e0 F=81f80000
op 19 sf 1: 9=fffffffe 10=7fff 11=ffffffff 20=1000 21=7f00ff00 22=7f00ff00 25=fffffffe 26=87ef 27=ffffffff 28=3e0 F=80b80000
op 19 sf 0: 9=ffff8000 10=7fff 11=ffff8000 20=1000 21=7fffff00 22=7f00ff00 25=fffef010 26=87ef000 27=fff7f010 28=3e0 F=81f80000
op 1A sf 1: 9=fffffffe 10=7fff 11=ffffffff 20=b3b04688 21=1000 22=7f00ff00 25=fffffffe 26=87ef 27=ffffffff 28=3e0 F=80b80000
op 1A sf 0: 9=ffff8000 10=7fff 11=ffff8000 20=b3b04688 21=1000 22=7f00ff00 25=fffef010 26=87ef000 27=fff7f010 28=3e0 F=81f80000
op 1B sf 1: 9=7f7f 10=ffffc080 11=ffff8080 20=b3b04688 21=1000 22=7f0000ff 25=7f7f 26=ffffc080 27=ffff8080 28=1f F=89f80000
op 1B sf 0: 9=7fff 10=7fff 20=b3b04688 21=1000 22=7fffffff 25=7f7f010 26=3f7f810 27=7f7f010 28=7fff F=c9f80000
op 1C sf 1: 9=ffff8080 10=ffffc080 11=ffff8080 20=b3b04688 21=1000 22=7f000000 25=ffff8080 26=ffffc080 27=ffff8080 28=0 F=81f80000
op 1C sf 0: 9=7fff 10=7fff 20=b3b04688 21=1000 22=7fffffff 25=7f7f010 26=3f7f810 27=7f7f010 28=7fff F=81f80000
op 1D sf 1: 9=7f7f 10=3f7f 11=7f7f 20=b3b04688 21=1000 22=7fffffff 25=7f7f 26=3f7f 27=7f7f 28=7fff F=380000
op 1D sf 0: 9=7fff 10=7fff 20=b3b04688 21=1000 22=7fffffff 25=7f7f010 26=3f7f810 27=7f7f010 28=7fff F=81f80000
op 1E sf 1: 9=7fff 10=ffff8000 11=ffff8000 20=b3b04688 21=1000 22=7f0000ff 25=7fffbc38 26=c6c54f47 27=91147f57 28=1f F=89f80000
op 1E sf 0: 9=7fff 10=7fff 20=b3b04688 21=1000 22=7fffffff 25=8008000 26=54f42001 27=11c8cc8d 28=7fff F=c9f80000
op 1F sf 1: 9=ffff8000 10=ffff8000 11=ffff8000 20=b3b04688 21=1000 22=7f000000 25=80008008 26=c6c54f42 27=91111c8c 28=0 F=c9f80000
op 1F sf 0: 9=7fff 10=7fff 20=b3b04688 21=1000 22=7fffffff 25=8008000 26=54f42001 27=11c8cc8d 28=7fff F=c9f80000
op 20 sf 1: 9=7fff 10=ffff8000 11=ffff8000 20=7f0000ff 21=7f0000ff 22=7f0000ff 25=7ffd9240 26=c6c54f44 27=9115b687 28=1f F=89f80000
op 20 sf 0: 9=7fff 10=7fff 20=7fffffff 21=7fffffff 22=7fffffff 25=8008000 26=54f42001 27=11c8cc8d 28=7fff F=c9f80000
op 21 sf 1: 9=ffff8000 10=ffff8000 11=ffff8000 20=7f000000 21=7f000000 22=7f000000 25=80000008 26=c6c54f39 27=9111a48f 28=0 F=c9f80000
op 21 sf 0: 9=7fff 10=7fff 20=7fffffff 21=7fffffff 22=7fffffff 25=8000 26=54f39001 27=1a48fc8d 28=7fff F=c9f80000
op 22 sf 1: 9=ffff8000 10=ffff8000 11=ffff8000 20=7f0000ff 21=7f000000 22=7f000000 25=80000008 26=c6c54f39 27=9111a48f 28=0 F=c9f80000
op 22 sf 0: 9=7fff 10=7fff 20=7fffff00 21=7fffffff 22=7fffffff 25=8000 26=54f39001 27=1a48fc8d 28=7fff F=c9f80000
op 23 sf 1: 9=ffff8000 10=ffff8000 11=ffff8000 20=7f002311 21=7f000000 22=7f000000 25=80000008 26=c6c54f39 27=9111a48f 28=0 F=c9f80000
op 23 sf 0: 9=7fff 10=7fff 20=7fff2311 21=7fffffff 22=7fffffff 25=8000 26=54f39001 27=1a48fc8d 28=7fff F=c9f80000
op 24 sf 1: 9=ffff8000 10=ffff8000 11=ffff8000 20=1000 21=7f000000 22=7f000000 25=80000008 26=c6c54f39 27=9111a48f 28=0 F=c9f80000
op 24 sf 0: 9=7fff 10=7fff 20=1000 21=7fffffff 22=7fffffff 25=8000 26=54f39001 27=1a48fc8d 28=7fff F=c9f80000
op 25 sf 1: 9=ffff8000 10=ffff8000 11=ffff8000 20=b3b04688 21=1000 22=7f000000 25=80000008 26=c6c54f39 27=9111a48f 28=0 F=81f80000
op 25 sf 0: 9=7fff 10=7fff 20=b3b04688 21=1000 22=7fffffff 25=8000 26=54f39001 27=1a48fc8d 28=7fff F=81f80000
op 26 sf 1: 10=ffff8000 11=ffff8000 20=b3b04688 21=1000 22=7f0000ff 26=c6c54f39 27=9111a48f 28=0 F=80d80000
op 26 sf 0: 10=7fff 20=b3b04688 21=1000 22=7fffffff 26=54f39001 27=1a48fc8d F=80d80000
op 27 sf 1: 11=ffff8000 20=b3b04688 21=1000 22=7f002311 27=9111a48f 28=3e0 F=480000
op 27 sf 0: 20=b3b04688 21=1000 22=7fff2311 27=1a48fc8d F=480000
op 28 sf 1: 9=0 25=0 26=1000 27=3fff0 F=400000
op 28 sf 0: 9=1 10=7fff 25=1 26=1000000 27=3fff0001 F=80c00000
op 29 sf 1: 9=fffffffe 10=7fff 11=ffffffff 20=b3b04688 21=1000 22=7f00ff00 25=fffffffe 26=87ef 27=ffffffff 28=3e0 F=80b80000
op 29 sf 0: 9=ffff8000 10=7fff 11=ffff8000 20=b3b04688 21=1000 22=7f00ff00 25=fffef010 26=87ef000 27=fff7f010 28=3e0 F=81f80000
op 2A sf 1: 10=7fff 11=0 20=7f00ff00 21=7f00ff00 22=7f00ff00 25=ffffffff 26=80ff 27=0 28=3e0 F=80b00000
op 2A sf 0: 9=ffff8000 10=7fff 11=0 20=7f00ff00 21=7f00ff00 22=7f00ff00 25=ff000000 26=80ff000 27=0 28=3e0 F=81f80000
op 2B sf 1: 10=7fff 11=0 21=7f00ff00 22=7f00ff00 25=ffffffff 26=80ff 27=0 28=3e0 F=80b00000
op 2B sf 0: 9=ffff8000 10=7fff 11=0 21=7f00ff00 22=7f00ff00 25=ff000000 26=80ff000 27=0 28=3e0 F=81f80000
op 2C sf 1: 10=7fff 11=0 22=7f00ff00 25=ffffffff 26=80ff 27=0 28=3e0 F=80b00000
op 2C sf 0: 9=ffff8000 10=7fff 11=0 22=7f00ff00 25=ff000000 26=80ff000 27=0 28=3e0 F=81b00000
op 2D sf 1: 7=0 24=ef21e181 F=80040000
op 2D sf 0: 7=0 24=ef21e181 F=80040000
op 2E sf 1: 7=0 24=c57ae939 F=80040000
op 2E sf 0: 7=0 24=c57ae939 F=80040000
op 2F sf 1: 7=0 9=7fff 10=7fff 20=7fffffff 21=7fffffff 22=7fffffff 24=dca18c84 25=8000 26=54f39001 27=1a48fc8d 28=7fff F=c9fc8000
op 2F sf 0: 7=0 9=7fff 10=7fff 20=7fffffff 21=7fffffff 22=7fffffff 24=45d48c84 25=8000 26=54f39001 27=1a48fc8d 28=7fff F=c9fc8000
op 30 sf 1: 8=0 9=ffff8000 10=7fff 11=ffff8000 12=3fffc00 13=3fffc00 14=3fffc00 16=c3a3 17=0 18=0 19=0 24=22632822 25=89c65e89 26=3b532619 27=8000c44b 28=3e0 F=81c7f000
op 30 sf 0: 8=0 9=7fff 10=7fff 12=3fffc00 13=3ff03ff 14=3ff03ff 16=c3a3 17=0 18=0 19=0 24=22632822 25=65e89000 26=32619148 27=c44b20b 28=7fff F=81c7f000
op 31 sf 1: 8=0 9=ffff8000 10=7fff 11=ffff8000 12=3fffc00 13=3fffc00 14=3fffc00 16=c3a3 17=0 18=0 19=0 24=22632822 25=89c65e89 26=3b532619 27=8000c44b 28=3e0 F=81c7f000
op 31 sf 0: 8=0 9=7fff 10=7fff 12=3fffc00 13=3ff03ff 14=3ff03ff 16=c3a3 17=0 18=0 19=0 24=22632822 25=65e89000 26=32619148 27=c44b20b 28=7fff F=81c7f000
op 32 sf 1: 8=0 9=ffff8000 10=7fff 11=ffff8000 12=3fffc00 13=3fffc00 14=3fffc00 16=c3a3 17=0 18=0 19=0 24=22632822 25=89c65e89 26=3b532619 27=8000c44b 28=3e0 F=81c7f000
op 32 sf 0: 8=0 9=7fff 10=7fff 12=3fffc00 13=3ff03ff 14=3ff03ff 16=c3a3 17=0 18=0 19=0 24=22632822 25=65e89000 26=32619148 27=c44b20b 28=7fff F=81c7f000
op 33 sf 1: 8=0 9=ffff8000 10=7fff 11=ffff8000 12=3fffc00 13=3fffc00 14=3fffc00 16=c3a3 17=0 18=0 19=0 24=22632822 25=89c65e89 26=3b532619 27=8000c44b 28=3e0 F=81c7f000
op 33 sf 0: 8=0 9=7fff 10=7fff 12=3fffc00 13=3ff03ff 14=3ff03ff 16=c3a3 17=0 18=0 19=0 24=22632822 25=65e89000 26=32619148 27=c44b20b 28=7fff F=81c7f000
op 34 sf 1: 8=0 9=ffff8000 10=7fff 11=ffff8000 12=3fffc00 13=3fffc00 14=3fffc00 16=e9f7 17=c3a3 18=0 19=0 24=22632822 25=89c65e89 26=3b532619 27=8000c44b 28=3e0 F=81c7f000
op 34 sf 0: 8=0 9=7fff 10=7fff 12=3fffc00 13=3ff03ff 14=3ff03ff 16=e9f7 17=c3a3 18=0 19=0 24=22632822 25=65e89000 26=32619148 27=c44b20b 28=7fff F=81c7f000
op 35 sf 1: 8=0 9=ffff8000 10=7fff 12=3fffc00 13=3fffc00 14=3ffff99 16=e9f7 17=c3a3 18=0 19=ffff 24=9b0151c0 25=89c65e89 26=3b532619 F=81c7f000
op 35 sf 0: 8=0 9=7fff 10=7fff 12=3ffff99 13=3ff03ff 14=3ff03ff 16=e9f7 17=c3a3 18=0 19=ffff 24=9b0151c0 25=65e89000 26=32619148 28=7fff F=81c77000
op 36 sf 1: 8=0 9=ffff8000 10=7fff 12=3ffff99 13=3ff03ff 14=3fffc00 16=29cd 17=e9f7 18=c3a3 19=0 24=22632822 25=89c65e89 26=3b532619 F=8183f000
op 36 sf 0: 8=0 9=7fff 10=7fff 12=3fffc00 13=3ff03ff 14=3ff03ff 16=29cd 17=e9f7 18=c3a3 19=0 24=22632822 25=65e89000 26=32619148 28=7fff F=8183f000
op 37 sf 1: 8=0 10=7fff 12=3fffc00 13=3ff03ff 14=3ff03ff 16=29cd 17=e9f7 18=c3a3 19=0 24=22632822 26=3b532619 F=8083f000
op 37 sf 0: 8=0 10=7fff 12=3fffc00 13=3ff03ff 14=3ff03ff 16=29cd 17=e9f7 18=c3a3 19=0 24=22632822 26=32619148 F=8083f000
op 38 sf 1: 8=0 10=7fff 12=3fffc00 13=3ff03ff 14=3ff03ff 16=29cd 17=e9f7 18=c3a3 19=0 24=22632822 26=3b532619 F=8083f000
op 38 sf 0: 8=0 10=7fff 12=3fffc00 13=3ff03ff 14=3ff03ff 16=29cd 17=e9f7 18=c3a3 19=0 24=22632822 26=32619148 F=8083f000
op 39 sf 1: 8=0 12=3fffc00 13=3ff03ff 14=3fffffe 16=29cd 17=e9f7 18=c3a3 19=0 24=22632822 F=8001f000
op 39 sf 0: 8=0 12=3fffc00 13=3ff03ff 14=3fffffe 16=29cd 17=e9f7 18=c3a3 19=0 24=22632822 F=8001f000
op 3A sf 1: 8=0 12=1000 13=3ff03ff 14=3fffffe 16=29cd 17=e9f7 18=c3a3 19=0 24=22632822 F=8001f000
op 3A sf 0: 8=0 12=1000 13=3ff03ff 14=3fffffe 16=29cd 17=e9f7 18=c3a3 19=0 24=22632822 F=8001f000
op 3B sf 1: 8=0 12=1000 14=3fffffe 24=22632822 F=8000b000
op 3B sf 0: 8=0 12=1000 14=3fffffe 24=22632822 F=8000b000
op 3C sf 1: 8=0 9=ffff8000 10=7fff 12=1000 14=3fffc00 16=29cd 17=e9f7 18=c3a3 19=0 24=22632822 25=cdadc000 26=42ced12c 27=14e522f2 F=81c7f000
op 3C sf 0: 8=0 9=ffff8000 10=7fff 12=1000 14=3fffc00 16=29cd 17=e9f7 18=c3a3 19=0 24=22632822 25=cdadc000 26=42ced12c 27=14e522f2 F=81c7f000
op 3D sf 1: 20=b3b04688 21=1000 22=7fffff00 25=ffffffff 26=1000 27=7fff F=380000
op 3D sf 0: 9=fffff000 10=7fff 20=b3b04688 21=1000 22=7fffff00 25=fffff000 26=1000000 27=7fff000 F=80f80000
op 3E sf 1: 9=7fff 10=ffff8000 20=b3b04688 21=1000 22=7fff00ff 25=53157f31 26=db67a9fc 27=43e637f3 28=7c1f F=81f80000
op 3E sf 0: 9=7fff 10=ffff8000 20=b3b04688 21=1000 22=7fff00ff 25=53156f32 26=dc6799fc 27=4be5a7f4 28=7c1f F=81f80000
op 3F sf 1: 9=7f7f 10=ffffc080 11=ffff8080 20=7f0000ff 21=7f0000ff 22=7f0000ff 25=7f7f 26=ffffc080 27=ffff8080 28=1f F=89f80000
op 3F sf 0: 9=7fff 10=7fff 20=7fffffff 21=7fffffff 22=7fffffff 25=7f7f010 26=3f7f810 27=7f7f010 28=7fff F=c9f80000
Done.

06FMD.txt

===== 06 FMD FU MDEC RESET COLOUR | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 800154CE
Reset timing: MDEC1 written 80000000h, then MDEC1 read eight times, each followed by
a timer 2 read (cycles since just before the write).
Idle, status after the reset write @ timer 2: 80040000@15 80040000@35 80040000@53 80040000@71 80040000@89 80040000@107 80040000@125 80040000@143
15 bit decode with the input full, nothing read, status after the reset write @ timer 2: E60400DF@15 80040000@35 80040000@53 80040000@71 80040000@89 80040000@107 80040000@125 80040000@143
Short decode counts by CPU (mdecout ODD's way): the 4bit/8bit block at 8 bit with its
tables, the step stream at 15 bit with its tables. Only `count` words are written.
8 bit, decode count 1, 1 words written: 48 words out, CRC A9DEB035, status 8204FFFF, first 8F9EA9AF last 118AFF72
8 bit, decode count 2, 2 words written: 32 words out, CRC F60B4B13, status 8204FFFF, first FFFB7B20 last 118AFF72
15 bit, decode count 4, 4 words written: 32 words out, CRC C2A8FA9D, status 8601FFFF, first 00000000 last 00000000
15 bit, decode count 5, 5 words written: 32 words out, CRC C2A8FA9D, status 8601FFFF, first 00000000 last 00000000
15 bit, decode count 6, 6 words written: 32 words out, CRC C2A8FA9D, status 8601FFFF, first 00000000 last 00000000
Colour matrix and clamp: one macroblock of DC-only blocks, Cr and Cb and all four Y as
given (10 bit DC values), quant table all 4, the standard scale table, unsigned, by CPU.
The first output word of each 8x8 quadrant at 24 bit and at 15 bit.
Cr -256 Cb -256 Y 0: 24 bit 192 words, 0000FF00 0000FF00 0000FF00 0000FF00; 15 bit 128 words, 03E003E0 03E003E0 03E003E0 03E003E0
Cr -256 Cb -64 Y 0: 24 bit 192 words, 0047E700 0047E700 0047E700 0047E700; 15 bit 128 words, 27A027A0 27A027A0 27A027A0 27A027A0
Cr -256 Cb 0 Y 0: 24 bit 192 words, 0080DC00 0080DC00 0080DC00 0080DC00; 15 bit 128 words, 43604360 43604360 43604360 43604360
Cr -256 Cb 64 Y 0: 24 bit 192 words, 00B9D100 00B9D100 00B9D100 00B9D100; 15 bit 128 words, 5F405F40 5F405F40 5F405F40 5F405F40
Cr -256 Cb 255 Y 0: 24 bit 192 words, 00FFB000 00FFB000 00FFB000 00FFB000; 15 bit 128 words, 7EC07EC0 7EC07EC0 7EC07EC0 7EC07EC0
Cr -64 Cb -256 Y 0: 24 bit 192 words, 5300C353 5300C353 5300C353 5300C353; 15 bit 128 words, 030A030A 030A030A 030A030A 030A030A
Cr -64 Cb -64 Y 0: 24 bit 192 words, 5347A253 5347A253 5347A253 5347A253; 15 bit 128 words, 268A268A 268A268A 268A268A 268A268A
Cr -64 Cb 0 Y 0: 24 bit 192 words, 53809753 53809753 53809753 53809753; 15 bit 128 words, 426A426A 426A426A 426A426A 426A426A
Cr -64 Cb 64 Y 0: 24 bit 192 words, 53B98C53 53B98C53 53B98C53 53B98C53; 15 bit 128 words, 5E2A5E2A 5E2A5E2A 5E2A5E2A 5E2A5E2A
Cr -64 Cb 255 Y 0: 24 bit 192 words, 53FF6B53 53FF6B53 53FF6B53 53FF6B53; 15 bit 128 words, 7DAA7DAA 7DAA7DAA 7DAA7DAA 7DAA7DAA
Cr 0 Cb -256 Y 0: 24 bit 192 words, 8000AC80 8000AC80 8000AC80 8000AC80; 15 bit 128 words, 02D002D0 02D002D0 02D002D0 02D002D0
Cr 0 Cb -64 Y 0: 24 bit 192 words, 80478B80 80478B80 80478B80 80478B80; 15 bit 128 words, 26302630 26302630 26302630 26302630
Cr 0 Cb 0 Y 0: 24 bit 192 words, 80808080 80808080 80808080 80808080; 15 bit 128 words, 42104210 42104210 42104210 42104210
Cr 0 Cb 64 Y 0: 24 bit 192 words, 80B97580 80B97580 80B97580 80B97580; 15 bit 128 words, 5DF05DF0 5DF05DF0 5DF05DF0 5DF05DF0
Cr 0 Cb 255 Y 0: 24 bit 192 words, 80FF5480 80FF5480 80FF5480 80FF5480; 15 bit 128 words, 7D707D70 7D707D70 7D707D70 7D707D70
Cr 64 Cb -256 Y 0: 24 bit 192 words, AD0095AD AD0095AD AD0095AD AD0095AD; 15 bit 128 words, 02760276 02760276 02760276 02760276
Cr 64 Cb -64 Y 0: 24 bit 192 words, AD4774AD AD4774AD AD4774AD AD4774AD; 15 bit 128 words, 25F625F6 25F625F6 25F625F6 25F625F6
Cr 64 Cb 0 Y 0: 24 bit 192 words, AD8069AD AD8069AD AD8069AD AD8069AD; 15 bit 128 words, 41B641B6 41B641B6 41B641B6 41B641B6
Cr 64 Cb 64 Y 0: 24 bit 192 words, ADB95EAD ADB95EAD ADB95EAD ADB95EAD; 15 bit 128 words, 5D965D96 5D965D96 5D965D96 5D965D96
Cr 64 Cb 255 Y 0: 24 bit 192 words, ADFF3DAD ADFF3DAD ADFF3DAD ADFF3DAD; 15 bit 128 words, 7D167D16 7D167D16 7D167D16 7D167D16
Cr 255 Cb -256 Y 0: 24 bit 192 words, FF0051FF FF0051FF FF0051FF FF0051FF; 15 bit 128 words, 015F015F 015F015F 015F015F 015F015F
Cr 255 Cb -64 Y 0: 24 bit 192 words, FF4730FF FF4730FF FF4730FF FF4730FF; 15 bit 128 words, 24DF24DF 24DF24DF 24DF24DF 24DF24DF
Cr 255 Cb 0 Y 0: 24 bit 192 words, FF8025FF FF8025FF FF8025FF FF8025FF; 15 bit 128 words, 40BF40BF 40BF40BF 40BF40BF 40BF40BF
Cr 255 Cb 64 Y 0: 24 bit 192 words, FFB91AFF FFB91AFF FFB91AFF FFB91AFF; 15 bit 128 words, 5C7F5C7F 5C7F5C7F 5C7F5C7F 5C7F5C7F
Cr 255 Cb 255 Y 0: 24 bit 192 words, FFFF00FF FFFF00FF FFFF00FF FFFF00FF; 15 bit 128 words, 7C1F7C1F 7C1F7C1F 7C1F7C1F 7C1F7C1F
Cr -256 Cb -256 Y -128: 24 bit 192 words, 00FFC800 00FFC800 00FFC800 00FFC800; 15 bit 128 words, 7F207F20 7F207F20 7F207F20 7F207F20
Cr -256 Cb -256 Y 127: 24 bit 192 words, 0C00FF0C 0C00FF0C 0C00FF0C 0C00FF0C; 15 bit 128 words, 03E103E1 03E103E1 03E103E1 03E103E1
Cr -256 Cb 255 Y -128: 24 bit 192 words, 00FF7000 00FF7000 00FF7000 00FF7000; 15 bit 128 words, 7DC07DC0 7DC07DC0 7DC07DC0 7DC07DC0
Cr -256 Cb 255 Y 127: 24 bit 192 words, 0C00EF0C 0C00EF0C 0C00EF0C 0C00EF0C; 15 bit 128 words, 03C103C1 03C103C1 03C103C1 03C103C1
Cr 255 Cb -256 Y -128: 24 bit 192 words, F2FF11F2 F2FF11F2 F2FF11F2 F2FF11F2; 15 bit 128 words, 7C5E7C5E 7C5E7C5E 7C5E7C5E 7C5E7C5E
Cr 255 Cb -256 Y 127: 24 bit 192 words, FF0090FF FF0090FF FF0090FF FF0090FF; 15 bit 128 words, 025F025F 025F025F 025F025F 025F025F
Cr 255 Cb 255 Y -128: 24 bit 192 words, F2FF00F2 F2FF00F2 F2FF00F2 F2FF00F2; 15 bit 128 words, 7C1E7C1E 7C1E7C1E 7C1E7C1E 7C1E7C1E
Cr 255 Cb 255 Y 127: 24 bit 192 words, FF0038FF FF0038FF FF0038FF FF0038FF; 15 bit 128 words, 00FF00FF 00FF00FF 00FF00FF 00FF00FF
Cr 0 Cb 0 Y -128: 24 bit 192 words, 40404040 40404040 40404040 40404040; 15 bit 128 words, 21082108 21082108 21082108 21082108
Cr 0 Cb 0 Y 127: 24 bit 192 words, BFBFBFBF BFBFBFBF BFBFBFBF BFBFBFBF; 15 bit 128 words, 63186318 63186318 63186318 63186318
Cr 64 Cb -64 Y -128: 24 bit 192 words, 6D07346D 6D07346D 6D07346D 6D07346D; 15 bit 128 words, 04EE04EE 04EE04EE 04EE04EE 04EE04EE
Cr 64 Cb -64 Y 127: 24 bit 192 words, EC86B3EC EC86B3EC EC86B3EC EC86B3EC; 15 bit 128 words, 46DD46DD 46DD46DD 46DD46DD 46DD46DD
Cr -64 Cb 64 Y -128: 24 bit 192 words, 13794C13 13794C13 13794C13 13794C13; 15 bit 128 words, 3D223D22 3D223D22 3D223D22 3D223D22
Cr -64 Cb 64 Y 127: 24 bit 192 words, 92F8CB92 92F8CB92 92F8CB92 92F8CB92; 15 bit 128 words, 7F327F32 7F327F32 7F327F32 7F327F32
Done.

07FSP.txt

===== 07 FSP FU SPU ENV FIFO | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 800154CE
Envelope counter, one for all voices or one each: voices 0 and 1 attack linear shift
16 step 0, keyed on 1500 cycles apart; cycles from voice 0's KON.
Voice 0 keyed on at 0, voice 1 at 1636; first level changes, voice 0: 24084 48652 73220 97764; voice 1: 24084 48652 73220 97764; levels then 002A 002A
Voice 0 keyed on at 0, voice 1 at 1605; first level changes, voice 0: 17803 42355 66923 91563; voice 1: 17803 42355 66923 91563; levels then 002A 002A
Voice 0 keyed on at 0, voice 1 at 1568; first level changes, voice 0: 17864 42408 66976 91528; voice 1: 17864 42408 66976 91528; levels then 002A 002A
ADSR level times the sample: tone T on voice 1, pitch 1000h, held at 7FFFh; the level
register written, then the voice 1 capture buffer (first 16 samples).
Level as it stands, 255 changes in 256:
  FC83 FD03 FD88 FE28 FEC5 FF57 FFE1 0062 00DB 014C 01B7 021B 0278 02D0 0322 036F
Level read 3FFF
Level written 4000h, reads 4000
Level 4000h, 255 changes in 256:
  00DB 014D 01B7 021B 0279 02D1 0323 0370 0392 02FF 024F 01AA 0110 007F FFF7 FF78
Level written 7FFFh, reads 7FFF
Level 7FFFh, 255 changes in 256:
  0724 05FD 049E 0354 021F 00FD FFEF FEF1 FE03 FD23 FC53 FB8E FAD5 FA29 FA94 FF31
FIFO drain: halfwords B000h, B001h, .. to scratch at 30000h (filled EEEEh) by one DMA
block of 16 words, a wait, SPUCNT transfer mode Stop, then read back by DMA.
Wait 0 cycles after the DMA ended: 9 of 32 halfwords written, 16 still EEEEh, first B000 last EEEE
Wait 100 cycles after the DMA ended: 9 of 32 halfwords written, 16 still EEEEh, first B000 last EEEE
Wait 200 cycles after the DMA ended: 10 of 32 halfwords written, 16 still EEEEh, first B000 last EEEE
Wait 300 cycles after the DMA ended: 15 of 32 halfwords written, 16 still EEEEh, first B000 last EEEE
Wait 400 cycles after the DMA ended: 19 of 32 halfwords written, 13 still EEEEh, first B000 last EEEE
Wait 500 cycles after the DMA ended: 23 of 32 halfwords written, 9 still EEEEh, first B000 last EEEE
Wait 600 cycles after the DMA ended: 27 of 32 halfwords written, 5 still EEEEh, first B000 last EEEE
Wait 700 cycles after the DMA ended: 31 of 32 halfwords written, 1 still EEEEh, first B000 last EEEE
Wait 800 cycles after the DMA ended: 32 of 32 halfwords written, 0 still EEEEh, first B000 last B01F
Wait 900 cycles after the DMA ended: 32 of 32 halfwords written, 0 still EEEEh, first B000 last B01F
Wait 1000 cycles after the DMA ended: 32 of 32 halfwords written, 0 still EEEEh, first B000 last B01F
Wait 1100 cycles after the DMA ended: 32 of 32 halfwords written, 0 still EEEEh, first B000 last B01F
Wait 1200 cycles after the DMA ended: 32 of 32 halfwords written, 0 still EEEEh, first B000 last B01F
Wait 1300 cycles after the DMA ended: 32 of 32 halfwords written, 0 still EEEEh, first B000 last B01F
Wait 1400 cycles after the DMA ended: 32 of 32 halfwords written, 0 still EEEEh, first B000 last B01F
Wait 1500 cycles after the DMA ended: 32 of 32 halfwords written, 0 still EEEEh, first B000 last B01F
Wait 1600 cycles after the DMA ended: 32 of 32 halfwords written, 0 still EEEEh, first B000 last B01F
Start address one 8 byte unit past a block (spuenv END's S4+8 case): tone T on voice 1,
pitch 1000h, start and repeat as given; the voice 1 capture buffer.
Start 40C0h (the block), 64 changes in 256:
  0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
  0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
Start 40C1h (one unit in), 255 changes in 256:
  FE29 FDC7 FD6A FD14 FD4A FF98 007E 00FE 017D 01FD 027C 02FC 024B FD30 FC83 FD03
  FD82 FE01 FE81 FF00 FF80 FFFF 007E 00FE 017D 01FD 027C 02FC 024B FD30 FC83 FD03
Done.

08FDS.txt

===== 08 FDS FU DMA SPU BLOCKS | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 800154CE
DMA4 SPU write SyncMode 1, 256 words to 30000h, cycles from the CHCR write until bit 24
clears, three times each. SPU delay register (1F801014h) was 200931E1.
Delay 200931E1, blocks of 1 words x 256: 16393 16343 16328
Delay 200931E1, blocks of 2 words x 128: 16327 16313 16313
Delay 200931E1, blocks of 4 words x 64: 18283 18279 18279
Delay 200931E1, blocks of 8 words x 32: 17082 17091 17091
Delay 200931E1, blocks of 16 words x 16: 16801 16801 16801
Delay 200931E1, blocks of 32 words x 8: 8502 8530 8530
Delay 210931E1, blocks of 1 words x 256: 16369 16351 16327
Delay 210931E1, blocks of 2 words x 128: 17739 17740 17740
Delay 210931E1, blocks of 4 words x 64: 18319 18302 18313
Delay 210931E1, blocks of 8 words x 32: 17921 17915 17915
Delay 210931E1, blocks of 16 words x 16: 17564 17529 17560
Delay 210931E1, blocks of 32 words x 8: 8578 8578 8578
Delay 220931E1, blocks of 1 words x 256: 16360 16349 16357
Delay 220931E1, blocks of 2 words x 128: 19587 19553 19553
Delay 220931E1, blocks of 4 words x 64: 18311 18308 18307
Delay 220931E1, blocks of 8 words x 32: 18639 18623 18623
Delay 220931E1, blocks of 16 words x 16: 17781 17735 17735
Delay 220931E1, blocks of 32 words x 8: 9486 9459 9478
Delay 230931E1, blocks of 1 words x 256: 18677 18550 18618
Delay 230931E1, blocks of 2 words x 128: 19575 19578 19578
Delay 230931E1, blocks of 4 words x 64: 19434 19445 19398
Delay 230931E1, blocks of 8 words x 32: 18650 18727 18644
Delay 230931E1, blocks of 16 words x 16: 17787 17741 17741
Delay 230931E1, blocks of 32 words x 8: 10222 10175 10175
SPU delay register back to 200931E1
Done.

09FSI.txt

===== 09 FSI FU SIO RXEN IMASK | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 800154CE
Controller port with RXEN and no device selected (JOY_CTRL bit 1 clear), slot 1.
CTRL 0004, no data written; JOY_STAT (bits 0-10) every 100 cycles from 0 to 3000:
  005 005 005 005 005 005 005 005 005 005 005 005 005 007 007 007 007 007 007 007 007 007 007 007 007 007 007 007 007 007 007
  bytes in the RX FIFO: 1 FF; I_STAT bit 7 then 0
CTRL 0805, no data written; JOY_STAT (bits 0-10) every 100 cycles from 0 to 3000:
  005 005 005 005 005 005 005 005 005 005 005 005 005 207 207 207 207 207 207 207 207 207 207 207 207 207 207 207 207 207 207
  bytes in the RX FIFO: 1 FF; I_STAT bit 7 then 1
I_MASK's upper half (the console read 960507FFh after sw FFFFFFFFh, chainb/028/01IMR.txt:4):
sw 12345678h to I_MASK, lw at once: AD090678
sw 12345678h, lui/ori of CAFEBABEh, then lw: AD090678
sw 12345678h, lw of I_STAT and a nop, then lw: AE020678
I_MASK back to 00000009
Done.

10FGR.txt

===== 10 FGR FU GPU RASTER | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 800154CE
GPU: the drawing offset's wrap, GP1(10h) upper bits, the C0h pad, two CLUT rows, and
last the time 42 unwaited GP0 stores take.
GPUSTAT 5606200F at the start
Tile 60h 16x1 red, drawing area x 64..95 on row 420:
Offset 0, vertex x 76 (the setup, no wrap): 16 of 32 drawn in x 64..95, first at x 76
  ............################....
Offset 500, vertex x 600 (sum 1100): 0 of 32 drawn in x 64..95
  ................................
Offset 1000, vertex x 100 (sum 1100): 0 of 32 drawn in x 64..95
  ................................
GP1(10h), whole words:
E1 0 (4 bit page at 0,0): E2 FFFFFFh, then index 2 five times: 000FFFFF 000FFFFF 000FFFFF 000FFFFF 000FFFFF; after reading 4 pixels (1230 1231 1232 1233): 123FFFFF
  E3 FFFFFFh, then index 3 five times: 123FFFFF 123FFFFF 123FFFFF 123FFFFF 123FFFFF; after reading the pixels again: 123FFFFF
E1 4 bit page at 512,256: E2 FFFFFFh, then index 2 five times: 123FFFFF 123FFFFF 123FFFFF 123FFFFF 123FFFFF; after reading 4 pixels (1230 1231 1232 1233): 123FFFFF
  E3 FFFFFFh, then index 3 five times: 123FFFFF 123FFFFF 123FFFFF 123FFFFF 123FFFFF; after reading the pixels again: 123FFFFF
E1 15 bit page at 768,256: E2 FFFFFFh, then index 2 five times: 123FFFFF 123FFFFF 123FFFFF 123FFFFF 123FFFFF; after reading 4 pixels (1230 1231 1232 1233): 123FFFFF
  E3 FFFFFFh, then index 3 five times: 123FFFFF 123FFFFF 123FFFFF 123FFFFF 123FFFFF; after reading the pixels again: 123FFFFF
GP0(C0h) pad halfword:
Row 408 all 2222h, row 409 all 3333h: C0h 3x1 at 100,408 reads 22222222 22222222; GPUSTAT then 56062000
Row 408 2220h, 2221h, .. 2227h, row 409 all 3333h: C0h 3x1 at 100,408 reads 22212220 22232222; GPUSTAT then 56062000
CLUT rows of gpuraster CLC, 256x1 sprites of row v 1 of the page at 576,256, CLUT at
256,y holding 4000h|i; texture cache cleared first:
15 bit mode (E1 depth 2), first 16 pixels: 0100 0302 0504 0706 0908 0B0A 0D0C 0F0E 1110 1312 1514 1716 1918 1B1A 1D1C 1F1E
Depth 3 (E1 bits 7-8 = 3), first 16 pixels: 0100 0302 0504 0706 0908 0B0A 0D0C 0F0E 1110 1312 1514 1716 1918 1B1A 1D1C 1F1E
8 bit, CLUT row overwritten with 7FFFh, second sprite with CLUT x 272 (+16), pixels 240..255: 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
  its pixels 0..15: 7FFF 7FFF 7FFF 7FFF 7FFF 7FFF 7FFF 7FFF 7FFF 7FFF 7FFF 7FFF 7FFF 7FFF 7FFF 7FFF
The zigzag polyline of 40 vertices, 42 GP0 stores with no wait: not run in this table.
Waits that ran out: 0
Done.

11FCD.txt

===== 11 FCD FU CD NO DISC | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 800154CE
CD-ROM, no disc: parameters left by an invalid command, Init's mode, Reset's deaf
window (last). Times are cycles from the command's write.
Switches (Test 21h, bit1 door open, bit0 head at POS0): int3 03 @29461. Getstat: int3 10 @29024. Mode 20. HINTMSK was 1F.
2 parameters then command 40h: int5 11 40 @22598; HSTS after its acknowledge 11; 0 cycles later HSTS 11; Getstat: int5 11 20 @33612
2 parameters then command 40h: int5 11 40 @22502; HSTS after its acknowledge 11; 10000 cycles later HSTS 11; Getstat: int5 11 20 @33415
2 parameters then command 40h: int5 11 40 @27494; HSTS after its acknowledge 11; 100000 cycles later HSTS 11; Getstat: int5 11 20 @27415
Init (0Ah): int3 10 @49233 | int2 10 @74801; Getparam then gives mode 20
Reset (1Ch), then a Getstat: not run in this table.
Reset (1Ch), then a Getstat: not run in this table.
Reset (1Ch), then a Getstat: not run in this table.
Reset (1Ch), then a Getstat: not run in this table.
Reset (1Ch), then a Getstat: not run in this table.
Reset (1Ch), then a Getstat: not run in this table.
Done.

28 September 2026 run 2

00RUN.txt

===== 00 RUN | BIOS 19951204 System ROM Version 3.0 11/18/96 A
1 tests
A chain program, linked at 80010000
Saved on the card in slot 2, from image 1
COP0 at start: BPC 00000000 BDA 80024F50 TAR 8010BEC0 DCIC 00000000 BadVaddr 1F801DAA BDAM FFFFFFFF
BPCM 00000000 SR 70000000 Cause 00000020 EPC 8010CA74 PRId 00000002

01FCD.txt

===== 01 FCD FU CD NO DISC | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 1F801DAA
CD-ROM, no disc: parameters left by an invalid command, Init's mode, Reset's deaf
window (last). Times are cycles from the command's write.
Switches (Test 21h, bit1 door open, bit0 head at POS0): int3 03 @24379. Getstat: int3 10 @30559. Mode 20. HINTMSK was 1F.
Reset (1Ch), then a Getstat:
  Reset: int3 10 @16892; Getstat sent at 50000: none
Reset (1Ch), then a Getstat:
  Reset: int3 10 @19530; Getstat sent at 100000: none
Reset (1Ch), then a Getstat:
  Reset: int3 10 @17036; Getstat sent at 200000: none
Reset (1Ch), then a Getstat:
  Reset: int3 10 @18672; Getstat sent at 300000: none
Reset (1Ch), then a Getstat:
  Reset: int3 10 @20636; Getstat sent at 600000: none
Reset (1Ch), then a Getstat:
  Reset: int3 10 @25630; Getstat sent at 1200000: none
Done.

28 September 2026 run 3

00RUN.txt

===== 00 RUN | BIOS 19951204 System ROM Version 3.0 11/18/96 A
1 tests
A chain program, linked at 80010000
Saved on the card in slot 2, from image 1
COP0 at start: BPC 00000000 BDA 80024F50 TAR 801125E4 DCIC 00000000 BadVaddr 1F801DAA BDAM FFFFFFFF
BPCM 00000000 SR 70000000 Cause 00000020 EPC 80113150 PRId 00000002

01FMR.txt

===== 01 FMR FU MDEC DMA RESET | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 1F801DAA
MDEC by DMA after a reset, then a CPU store to a full input FIFO. Each step saves the
log first.
One decode by DMA, the reset writes, then DMA0 alone: not run in this table.
A 33rd input word with bit 30 set:
  32 words written while bit 30 was clear, status E60400DF; the next word's store between timer 2 7 and 28; status then E60400DF; 0 words read out after, last 00000000, status E60400DF
Done.

28 September 2026 run 4

00RUN.txt

===== 00 RUN | BIOS 19951204 System ROM Version 3.0 11/18/96 A
1 tests
A chain program, linked at 80100000
Saved on the card in slot 2, from image 1
COP0 at start: BPC 00000000 BDA 80024F50 TAR 800225E0 DCIC 00000000 BadVaddr 1F801DAA BDAM FFFFFFFF
BPCM 00000000 SR 70000000 Cause 00000020 EPC 8002314C PRId 00000002

01FMR.txt

===== 01 FMR FU MDEC DMA RESET | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 1F801DAA
MDEC by DMA after a reset, then a CPU store to a full input FIFO. Each step saves the
log first.
One decode by DMA, the reset writes, then DMA0 alone:
  Tables by DMA0: quant 16 words 143, scale 32 words 95; mono 8 bit decode of 1 block to DMA1: output word 0 80808080, status 8204FFFF
  Reset 80000000h: status 8204D6E0
  MDEC1 80000000h: status before 82000000, after 80040000
  MDEC1 60000000h: status before 80040000, after 80040000
  MDEC0 40000000h: status before 80040000, after B004000F
  DMA0 alone, 16 words of quant: 77, 1 polls; status 8004FFFF, CHCR0 00000201 BCR0 00000010 MADR0 start64
A 33rd input word with bit 30 set: not run in this table.
Done.

28 September 2026 run 5

00RUN.txt

===== 00 RUN | BIOS 19951204 System ROM Version 3.0 11/18/96 A
1 tests
A chain program, linked at 80100000
Saved on the card in slot 2, from image 1
COP0 at start: BPC 00000000 BDA 80024F50 TAR BFC02BAC DCIC 00000000 BadVaddr 1F801DAA BDAM FFFFFFFF
BPCM 00000000 SR 70000000 Cause 00000020 EPC 8001F08C PRId 00000002

01FGR.txt

===== 01 FGR FU GPU RASTER | BIOS 19951204 System ROM Version 3.0 11/18/96 A
BadVaddr as the group starts: 1F801DAA
GPU: the drawing offset's wrap, GP1(10h) upper bits, the C0h pad, two CLUT rows, and
last the time 42 unwaited GP0 stores take.
GPUSTAT 5606200F at the start
The zigzag polyline of 40 vertices, 42 GP0 stores with no wait:
  42 stores took 535 cycles, the GPU idle by 86883; crc 052D62B7, 64 drawn
Waits that ran out: 1
Done.

References

  1. ^ a b c d e f g h i j k l m n o p q r s t u v w x y z SCPH-5501 output: followup/00RUN.txt and the files beside it, with the other runs listed under Runs.

Categories: Hardware tests